Parallella Community

I'm sorry, English is difficult for me...
again,
Is it possible to let the host (or the eCore) kicks off the DMA from ERAM to SRAM?

Any chance you could share your transfer bandwidth benchmark code?
-Ivan

I'd imagine those results are from e_dma_copy, copying about 6KB of data (DMA doesn't need to read instructions, so makes the best use of available memory bandwidth).

Have you had a look through the Adapteva and Embecosm repositories on Github? It's a goldmine! I haven't specifically seen this example there, but you may be in luck.

Regarding latency, there are effectively 3 memory tiers - internal SRAM, other cores' SRAM, and external DRAM. Other than accesses to internal SRAM the memory reads and writes are routed via the on-chip mesh metwork, and external memory accesses go via an off-chip interface, via the FPGA, to the DRAM chip.

Internal RAM is IIRC single-cycle for read and write, but for off-core accesses the latency increases with the number of hops across the mesh - see the documentation for details. External memory latency is going to be affected by a combination of mesh latency, DRAM speed (+ effects of contention with the host program), and speed of the interface between Epiphany and FPGA. Given the number of variables, if you wanted to know you'd have to measure it!* But the consensus seems to be that external RAM reads are a major bottle-neck.

I'm not a hardware guy so may have got the wrong end of the stick here, but if you study the documentation I think you'll get most of the answers you're looking for.

* (possible measurement approach: start a single-word DMA transfer and count the number of cycles until the completion interrupt. There is a DMA setup overhead but this can be factored out by measuring the time taken for a word to be read from an adjacent core).