Does parallella perform any power saving?

[fmotta]

Often clock or power gating is used for reducing the power consumption of a chip by "turning off/down" logic that is not in use.
This power scaling can also be made available for program control.

So, is there any simple power-management logic in parallella that shuts down logic not in use?
Is there program controlled power-down capability?
Additionally, if code is not started on a core then can it remain in low power mode?

Thanks

[charles]

Arch Reference, p45

ACTIVE
When set, it indicates that core is currently active. The core is inactive at reset and is activated by an external agent asserting an interrupt. Once activated, the core stays active until the user asserts the IDLE instruction, at which time the core enters a standby state. During the standby state, core clocks are disabled and the power consumption is minimized. Applications that need minimal power consumption should use the IDLE instruction to put the core in a standby state and use interrupts to activate the core when needed.

[fmotta]

@charles Thanks. So it appears that the cores a]start in low power mode and can self-power save. Can another core or a control-plane processor assert low power externally or does the core have to have some IPC message to execute an IDLE instruction thereby costing an undetermined amount of time for message passing (presuming traditional shared-memory based IPC)?

[aolofsson]

The power saving is done automatically by the core. In most application is well written there should be no need for another core to assert a low power state by force. The gentle way to take a core out of an active code loop and put him in a sleep state is through an interrupt.(writing to the core ILATST register)

[fmotta]