Parallella Community

I've been working with Network Simulators using NS3, more specifically mesh grid networks of chips.

I was wondering if the Parallella community have interest on an open-source simulator of the Epiphany NoC (eMesh) based on NS3, and what features one would expect to have there. In other words, which metrics to extract, and which scenarios to simulate.

It is already under development, and comments and contributions are very welcome.

The Epiphany Chip should be the first one to be implemented in order to validate the simulator.

Work done so far can be seen at: https://bitbucket.org/joaofl/noc

Thanks in advance.

Best,

João Loureiro

I would be most interested in a comparison between 16 and 64 core network performance (since most people don't have 64 cores) for various communication patterns (raster scan, rotate east/west/north/south, random, etc). I would also like a comparison to a much larger NoC. It would be good to know when the bandwidth/latency performance turns over for DMA and memory mapped access for both read and write operations (eventually, DMA is always faster, but how much data?). And if you're a glutton for punishment, performance of hypothetical tiled NoCs.

I would be interested in reading about your simulation results and how they compare to hardware (at least the 16-core NoC)