Parallella Community

You can easily synchronize all cores on the Epiphany chip. But since the bandwidth between the host and the Epiphany chips is limited, it makes more sense to synchronize only a single core with the host (and have that core synchronize with all other cores inside the Epiphany system, then).

Hi Sebera,

Thank you very much! So you means that it is the same if we just use me.corenum == 1 or 2 or 3 ... with the me.corenum == 0 ? Since we only need one core to be synchronize with the host and that core doesn't need to be the core 0 ? Here is my understanding, if anything is wrong, hope you can tell me ! Thank you all the same!

Best Regrads,
Richard

I guess it makes sense to pick one of the cores 0 - 3, to avoid the traffic having to pass through other cores on the way to its destination.

As far as I understand it, the external memory is located next to core 15 (bottom right).

Take with a grain of salt, what I write now. I haven't tested it.

Inside the Epiphany, bandwidth is generally sufficient (our problem is the memory size and as a consequence of too little buffering, latency; not data throughput). To my understanding, the NoC routers queue at most one transaction per direction. So, if your top-left core writes many packets to shared memory, then these transactions will queue up at each affected intersection and basically kill all traffic on that path. So it is probably beneficial to designate the bottom right core for off-chip (shared memory) transactions.

All 4 cores on right side are equidistant from dram. They all go through one 4:1 mux before going out on elink to the fpga.

Ah, thanks for the clarification!