Epiphany memory map
Posted: Tue Dec 08, 2015 6:56 am
Hello,
I'm very new to Parallella board and Epiphany chip, so I'd have some questions about both the chip and the board.
I've read some documentation, and have some remaining questions.
Could anyone confirm that each byte in the 32 KB local memory can be accessed by two addresses? The first, local address, is with the 12 high order bits set to zero, in the range 0-1 MB. The second is with the core's position in the grid set in the 12 high order bits, with the same values for the low order bits.
If this is correct, then how can be accessed the memory of core (0,0) by any other core? Because then the external addresses are confused with the local ones for each core.
Thank for your answers!
I'm very new to Parallella board and Epiphany chip, so I'd have some questions about both the chip and the board.
I've read some documentation, and have some remaining questions.
Could anyone confirm that each byte in the 32 KB local memory can be accessed by two addresses? The first, local address, is with the 12 high order bits set to zero, in the range 0-1 MB. The second is with the core's position in the grid set in the 12 high order bits, with the same values for the low order bits.
If this is correct, then how can be accessed the memory of core (0,0) by any other core? Because then the external addresses are confused with the local ones for each core.
Thank for your answers!