Bare metal application with FPGA co-processor

Any technical questions about the Epiphany chip and Parallella HW Platform.

Moderator: aolofsson

Re: Bare metal application with FPGA co-processor

Postby aolofsson » Fri May 20, 2016 6:48 pm

Great stuff. Thanks for posting this on the forum!

Timing paths:
Based on where those paths are, those paths go to the reset synchronizer. I probably declared those as false paths and forgot to check them in to the constraints back in the fall.

Master:
Master branch needs to be updated to new oh modules for fifos. (either a path issue or a module rename issue)

Yes, your summary sounds good.

Andreas
User avatar
aolofsson
 
Posts: 1005
Joined: Tue Dec 11, 2012 6:59 pm
Location: Lexington, Massachusetts,USA

Re: Bare metal application with FPGA co-processor

Postby eliaskousk » Fri May 20, 2016 7:20 pm

Andreas thank you for the quick reply.

So it seems I have built a good bitstream with vivado 2015.4 and this version can be used for Parallela bitstreams.

Can't wait to try it out on the board!

Best,
Elias
eliaskousk
 
Posts: 3
Joined: Mon Apr 25, 2016 10:17 am

Previous

Return to Epiphany and Parallella Q & A

Who is online

Users browsing this forum: No registered users and 15 guests