Re: Bare metal application with FPGA co-processor
Posted: Fri May 20, 2016 6:48 pmGreat stuff. Thanks for posting this on the forum!
Timing paths:
Based on where those paths are, those paths go to the reset synchronizer. I probably declared those as false paths and forgot to check them in to the constraints back in the fall.
Master:
Master branch needs to be updated to new oh modules for fifos. (either a path issue or a module rename issue)
Yes, your summary sounds good.
Andreas
Timing paths:
Based on where those paths are, those paths go to the reset synchronizer. I probably declared those as false paths and forgot to check them in to the constraints back in the fall.
Master:
Master branch needs to be updated to new oh modules for fifos. (either a path issue or a module rename issue)
Yes, your summary sounds good.
Andreas