IP Protection for Algorithms

Any technical questions about the Epiphany chip and Parallella HW Platform.

Moderator: aolofsson

IP Protection for Algorithms

Postby saialluru » Wed Aug 24, 2016 8:27 am

Hi,

I came across parallela while researching FPGA, while don't have much background in FPGA, have been researching to implement an algorithm with parallelism characteristics in FPGA, in a way to protect IP, in additions to performance. What my thought about IP protection is that I can create an encrypted bitstream and provision the FPGA, which make it difficult for others to gain access and protect algorithm from various attacks.

What I want to understand is if I implement the algorithm is C/C++, which is much easier than HDL for us, targeting Epiphany what options do I have ti protect the IP. Could I store the C Program as bitstream in FPGA and have the Epiphany load the program from the FPGA, would there be a concern of side channel attacks.

I am new to both FPGA and Parallella but conceptually how I can use Parallellla at the same time get protecting from my IP.

Thanks,
saialluru
 
Posts: 1
Joined: Wed Aug 24, 2016 7:39 am

Re: IP Protection for Algorithms

Postby sebraa » Thu Aug 25, 2016 11:57 am

The Epiphany is not suited for security-critical applications. The host program can always stop all cores and read each core's memory.
sebraa
 
Posts: 495
Joined: Mon Jul 21, 2014 7:54 pm


Return to Epiphany and Parallella Q & A

Who is online

Users browsing this forum: No registered users and 1 guest

cron