DRAM and SPM Access Latency
Posted: Tue Mar 07, 2017 2:05 am
The memory micro benchmarks provided in the Epiphany examples measure the bandwidth of copying data from DRAM to SPM. However, I am interested is finding the latency.
I want to find the access latency for obtaining 4 bytes of data by directly reading from off-chip DRAM (VS) reading it from local SPM. Is 1 cycle for local SPM access and 100 cycles for reading directly from off-chip memory a reasonable value?
Thanks a lot in advance.
I want to find the access latency for obtaining 4 bytes of data by directly reading from off-chip DRAM (VS) reading it from local SPM. Is 1 cycle for local SPM access and 100 cycles for reading directly from off-chip memory a reasonable value?
Thanks a lot in advance.