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Technical Details Epiphany-V

PostPosted: Tue Mar 14, 2017 9:25 am
by stefanluik
Hello,
could you tell some details about the chip ?
- Package size
- 16-bit external chip-addressing ?
- connection speed

Thanks
Stefan

Re: Technical Details Epiphany-V

PostPosted: Sat Apr 01, 2017 6:08 am
by olajep
Hi,

Some of the info is available in the Epiphany-V Technical Report:

https://www.parallella.org/2016/10/05/e ... processor/
https://www.parallella.org/wp-content/u ... re_soc.pdf

stefanluik wrote:- 16-bit external chip-addressing ?

I don't understand this question.

stefanluik wrote:- connection speed

Total chip IO Bandwidth: 192 Bytes / IO clock cycle

// Ola

Re: Technical Details Epiphany-V

PostPosted: Sat Apr 01, 2017 9:57 am
by dobkeratops
what would a ballpark "IO Clock Cycle" be, I understand you may want to clock it at different rates

is the potential bandwidth the same for GPIO and inter-chip links

Re: Technical Details Epiphany-V

PostPosted: Sat Apr 01, 2017 11:31 am
by olajep
dobkeratops wrote:what would a ballpark "IO Clock Cycle" be, I understand you may want to clock it at different rates

Probably enough ;) (sorry I'm not going to speculate).

dobkeratops wrote:is the potential bandwidth the same for GPIO and inter-chip links


In real world applications perhaps maybe guestimate an order of magnitude slower.
There's also a raw data streaming mode in the MIO block, so for higher frequencies you'd probably use that.

Re: Technical Details Epiphany-V

PostPosted: Mon Apr 03, 2017 9:29 am
by stefanluik
thanks for replies,
I want just some secured infos:
- 1 billion processors are 1.000.000.000 processors. right ?
- what space is needed for the total chip ? what form factor (bga ...) is the total chip ?
- what will be the momentan thinking speed in GHz of the connection ports to neighbour chip ?

This infos are just for planning / designing a system like a supercomputer.

Thanks for

Re: Technical Details Epiphany-V

PostPosted: Mon Apr 03, 2017 10:58 am
by sebraa
I do not think you will get any secured infos. But I can speculate (since I am not with Adapteva and have never been). :-D

A billion according to the US is 1.000.000.000.
Epiphany G3 and G4 chips are only available in BGA, so I would assume the same for G5. If they will be available to the public at all.
Given the 1024 GPIO signals specified, you can infer a reasonable package size.
The interconnect clock rate will be limited by the same physics that any other system has to deal with.

Do not expect miracles, only good engineering.