Schematic/Spec Review

Any technical questions about the Epiphany chip and Parallella HW Platform.

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Schematic/Spec Review

Postby aolofsson » Tue Jul 02, 2013 9:42 pm

Hi all,

As you probably saw we have published the latest spec and the early schematic this week. The new completed schematic will be published for review later this week. I think there are some pretty good improvement compared to the previous version, but we could really use your help in double checking our work to make sure there aren't any subtle issues.(urgently!)

Review needed among other things:
1.) power sub-system
2.) pec_power pin listing
3.) The experimental power rails on the pec_power. Anything we missed?
4.) The adc input

NEW Spec:
https://github.com/parallella/parallell ... erence.pdf

New Schematic:[edited, new schematic just came in...]
https://github.com/parallella/parallell ... ematic.pdf

Look forward to the feedback!

Andreas
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Re: Schematic/Spec Review

Postby ticso » Tue Jul 02, 2013 11:46 pm

I'm a bit confused by the different elink termination in gen0 schematic.
Especially between south/north, which both are routed to connectors.
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Re: Schematic/Spec Review

Postby ticso » Tue Jul 02, 2013 11:49 pm

Did I get it right, that Turbo_mode is just output to connector?
If there is any other relation by power selection I'm a bit worried when driven by 5V via PEC (or mount hole).
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Re: Schematic/Spec Review

Postby aolofsson » Wed Jul 03, 2013 2:08 am

@tisco Thanks for the feedback!

1.) I just published the latest schematics on github, the link is in this thread.(Note that there was a bug inserted on the TURBO_MODE, missing pull down, that I had missed in the review. Thanks for causing me to look at it again!!!)

2.) You are right to be worried about driving 5V from the mounting hole/PEC. :D This should definitely not be for the average user. They should all be using a 5V DC adapter through the barrel connector.

3.) The TURBO_MODE signal is a static signal that can be used as an input to FPGA logic or the daughter card to indicate how much "current" is available.

4.) The eLink termination might look confusing because of the different build option. The E16 and E64 have slightly different pinouts so we have to play around with extra DNI resistors to make sure we can build up both versions using a single PCB.

Andreas
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Re: Schematic/Spec Review

Postby ticso » Wed Jul 03, 2013 8:09 am

Pull down. Good you mention it, because I oversaw that the 125 is enable driven.
I see that the power switch circuit has been replaced with a jumper. This makes things easier.
Different epiphany pinout - does it mean the PEC pinout is different as well between 16 and 64 cores?
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Re: Schematic/Spec Review

Postby aolofsson » Wed Jul 03, 2013 11:13 am

Yes, the PEC pinout is different for the 16 and 64 core versions. This shown in the PEC_SOUTH and PEC_NORTH chapter for the Parallella manual.
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Re: Schematic/Spec Review

Postby timpart » Thu Jul 04, 2013 1:22 pm

On PEC Power there are DSP_XIDn and DSP_YIDn inputs to set the position of the Epiphany chip in a larger array of boards. Could these also be routed to some otherwise unused pins on the FPGA as well please so that chip knows where the board is too?

Otherwise I'm not sure how the ARM cores can determine the memory address to use to reach their local Epiphany. (If they try looking for chips at various addresses the North South links will route the request to that Epiphany and the ARM cores won't have a clue which is theirs.) The coordinates might also be useful to set the location of the external RAM with Epiphany addresses that match the position in the array.

If there is a shortage of GPIO pins I'd prioritize the signals in the order Y0, Y1, X0, Y2, Y3, X1, X2, X3.

Thanks,

Tim
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Re: Schematic/Spec Review

Postby aolofsson » Thu Jul 04, 2013 2:28 pm

Hi Tim,

Good point! There are unfortunately zero pins available on the FPGA and I am not sure it would be a good idea to hard code those pins on the Parallella board. You could route the XID/YID pins on a daughter card or with some wire wrap to the GPIO pins on the PEC_GPIO connector to get the effect you are looking for.

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Re: Schematic/Spec Review

Postby sievans » Thu Jul 11, 2013 6:36 am

Hi Andreas,

I noticed the 1V supply for the Zynq is rated at 1.5A. Have you seen the reports of larger than expected
draw on that rail on the Zedboard (e.g. http://www.zedboard.org/content/1v-powe ... er-powered
and http://www.zedboard.org/comment/3020#comment-3020)?

I haven't run into this myself on the Zedboard and I'm sure the standard design for the Parallela won't have
issues but wondering if it could be a problem if the logic is modified by users.

Cheers,
Si
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Re: Schematic/Spec Review

Postby tnt » Thu Jul 11, 2013 6:59 am

Haha, that second thread is me, burning the parallella prototype ...
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