Parallella Community

Hello,

In the "parallella gen1 reference", page 38, it is stated that Peak Zynq Frequency is 667 MHz.

The Zynq device used in parallella is XC7Z020-1CLG400C, so this is a -1 speed grade device, the slowest available (yes, I know that some -1 devices can actually operate at -2 or even -3 speed grades, but that is not guaranteed, Xilinx guarantee a -1 device to work at only -1 speed grades).

According to "Zynq-7000 All Programmable SoC (XC7Z010 and XC7Z020): DC and AC Switching Characteristics", page 36: CLB Switching Characteristics, we see that for speed grade -1, the slowest switching time in Table 57 is 1.27 ns which gives a max. freq. of 787.4 MHz. (I do know that different components in the FPGA operate at different freq., e.g. the DSP slices have a max. freq. of 464 MHz, but that's not the point).

The ARM processor operate at 667 MHz.

So it seems that we are operating both the FPGA's and the ARM processors at the same freq. even though the FPGA can reach higher freq., right? (by "FPGA", I am at least referring to the CLB and not to the I/O, DSP Slices, etc, although I know that this is practically not useful).

ali8

Nope.

The switching frequency for a Logic block is how quickly an input signal is acted on and becomes a stable output signal. On top of this you have to allow the time for routing the signals between logic blocks, that you may have more than one block between the source and target registers, and allow for clock skews and so on.

As a concrete example, I've made a fractal view that runs on a Zedboard (Zynq-7020) using just the programmable logic. It uses the FPGA's multipliers a lot. Although the multipliers are rated at about 490MHz on the datasheet the static timing for my design is 280MHz (although that isn't bad for using about 60 multipliers).

On this class of FPGA routing delays usually dominate a designs Fmax.

Oh I see, so I was neglecting how the signal comes in the first place to the CLBs...

Yes, we need to look at the minimum value since it will be the bottle nick...

Thank you.

There is no "minimum" values. You could make a design that can only run at 1 MHz if you wanted to ...

It's up to you to make your FPGA design properly to reach the frequency you target and only the Xilinx tools will be able to tell you if it met your objectives or not after syntesis and implementation ...

@hamster

Thanks for that example.