i was curious as to how RAW and WAW hazards are known to an instruction. as far as i can figure, there are 64 bits to mark for which registers are being read and another 64 for which register will be written to by the previous instruction. then this lock is checked against the current instruction until the ones to be used are freed up (by the last instruction) at which point it proceeds with the current instruction.
is this correct or perhaps there is just a single set of 64 bits which ends up blocking RAR? is there a better way to do this?
anyway it goes, do instructions get delayed and then lock registers at the beginning RA pipeline stage?