Parallella Community

So the Epiphany architecture doesn't currently have double-precision operations. I am no hardware design expert so I'll just assume that there are good reasons that they're missing from the architecture at the moment.

Double-precision operations are, however, important for many platforms to be ported to Epiphany. For example, in Erlang, the float type is always a 64-bit floating point value, meaning that all floating point operations on Epiphany cores would have to be emulated, defeating much of the purpose of having an FPU there in the first place.

So are there any plans for double-precision operations?

As stated at the end of section 7.2 of the :
"Double-precision floating-point arithmetic is emulated using software libraries and should be avoided if performance considerations outweigh the need for additional precision."

Or wait for Parallella V........

Yes, I know that the fallback is a soft float implementation. What I'm looking for is an official word on double-precision floating point plans, if there are any.

nm

gravis, It's probably better if you let someone from Adapteva answer Epiphany product road-map related questions. We're not always responsive, but no answer is better than giving the wrong answer.

alexrp, Double precision floating point has been been on our road-map for a while and the design is mostly done waiting for a customer. Initial plans was for a double precision chip to be taped out this year, but we got side tracked with the Parallella project. Once we get the Parallella board safely into production and distribution, we will get going on the Epiphany-V chip which will support double precision floating point.

Andreas

Andreas,
One question (and I know caveats about future products definitely apply!): are you looking at shipping the E-V with double precision as a 16 or 64 core part? And will it be on 28nm @ 1GHz? This is another feature I'm really interested in; feel free to message me with an answer (or non-answer) if more appropriate.
Thanks
-frank