1V regulator

[kcarnold]

I almost pre-ordered, but wavered on it and missed the cut-off But in the mean time, I noticed that the 1V power regulator for the Zynq is rated even lower than the Zedboard, and people have already encountered problems with that (see "1V Power supply under-powered" on their forums). We were planning on actually using the Zynq for some real processing, so if you're tweaking the board design, it would be really helpful if you could sneak in a regulator boost too.

(For reference, the Altera SoCKit puts an 8A regulator on their FPGA fabric. Granted the FPGA is not the star of this show, but it would still be nice to be able to use all it's got.)

[msegado]

Any plans to change this in a future revision?
Thanks!

(FYI, here's the thread that kcarnold mentioned about the Zedboard's bigger supply being underpowered, plus a more recent one:)
http://www.zedboard.org/content/1v-powe ... er-powered
http://www.zedboard.org/content/1v-power-supply-issues

[tnt]

From a previous thread this seems unlikely to happen just because there are no PMIC as small as the ones used now that could provide that much current.

However the board now has a proper connection point so you can feed 1V externally if needed.

[aolofsson]

As tnt noted, given all the constraints, and the fact that only a small number of people needed more than 1.5A on the 1P0V rail, the on-board regulator is not going to be made any beefier.

We did make a change to the gen 1.1/1.1 board due to feedback from folks with intent to really beat up on this board. The through-hole in question is TP13 and the picture below shows that this power might just be good enough to feed more current to the Zynq. Since this is very much an experimental feature, we need help testing it. Since the board runs quite hot with 5 Watt, cooling is going to be a an even bigger concern as you use even more of the Zynq device.

NOTE: You MUST ground the REG_EN1 through the PEC_POWER connector input if you are going to drive power directly to TP13 from an external supply. If you don't, you WILL break the board.

Andreas

[mark03]

I read through the ZedBoard community discussion on the spontaneous resets. While I am still concerned, I think it should be noted that we still don't have a smoking gun. Despite repeated pleas by the board designers, no one was willing (or paying enough attention?) to step forward with (1) their Verilog/VHDL design, and (2) the corresponding XPE (Xilinx Power Estimator) calculation. Those things would be the most basic, fundamental prerequisites to take this issue seriously and open a real investigation, yet they still don't have them ~6 months after the claim was initially made.

Granted, it's hard to imagine what else could explain the symptoms they were seeing, but it's possible that their PL design was really pathological in some way or another. I'm hopeful that this won't be a huge issue on my Z7020 Parallella... fingers crossed! And if it is, at least we can provide the data to Xilinx that the Zedboard community couldn't.

[msegado]

Wonderful, thanks all! Yes, keeping the PMIC as-is but making the 1V0 rail accessible seems like a good design move - thanks for including this =)

[solardiz]

[solardiz]