Parallella Community

Issuing the instruction outside an ISR obviously makes little sense, but what should actually happen? This is not currently documented.

I'd also like to point out that "Not specified" can be on purpose. That can mean the behavior should not be relied upon and can be subject to change in future silicon revisions.

alex,
As tim and others guessed, the RTI instruction does not care if the program is in an ISR or not.(as a lowly hardware designer I had to think about what that meant:D)

This is what happens when an RTI instruction is executed:

1.) the PC jumps to the address in the IRET register

2.) status[1] is cleared, enabling interrupts

3.) The IPEND bit of the ISR currently being executed is cleared. If the IPEND register is all zero (no ISR), there is nothing to clear.

4.)...undocumented, untested, and unsupported....status[2], user/kernel mode is set to user mode=0. (you can probably ignore this for now, I can give more information if someone thinks a user/kernel mode might be useful..) To enable user/kernel mode, set bit [25] of the CONFIG register.

Andreas

Thanks for the info Andreas. I have a more academic curiosity about kernel mode. I'm guessing it write protects certain important register bits. The changing back from user to kernel mode and the RAM bank write protection bits are the obvious candidates.

Alex, there is a separate Epiphany Operating System forum where you may be able to find like minded people.

Tim

Any chance the user / kernel mode status is passed along on off-chip memory access transactions?

all,
Since there seems to be some indication that it could be useful, I'll write up the chapter about the experimental user/kernel mode and SWI sometime in January after we get the board production solidly underway. Examples of things restricted in user mode include among other things: RTI,GIE,GID, and writing to MMRs.
Andreas