by aolofsson » Thu Jan 02, 2014 3:58 am
Writing a 1 to bit [0] of the RESETCORE register will put the core in a reset state. Writing a 0 to bit[0]of the RESETCORE register takes it out of reset. We chose not to document this register because we currently recommend that the whole system is reset together. If users start resetting cores while other cores are starting to access that core,then the eMesh can get locked up. There is also the issue of outstanding transactions returning to the core after RESET has been deasserted. The RESETCORE "reset" has the same effect as hardware reset, but to a reduced set of logic. At reset,the following happens:
-certain registers are reset to their reset values (as specified in the register table). This includes among other things the PC, STATUS, CONFIG,IRET,ILAT, etc.
-All internal hidden core state machines are reset (not visible to user)
-After reset, the core is idle (STATUS[0]=0) waiting for an interrupt to get started.