What makes the FPGA wheels turn

[theover]

HI,
I didn't receive my beloved little board yet, but I'm wondering about adding logic to FPGA.

From experience, it's not always trivial how to connect more logic to a processor/FPGA logic, by that I
mean it's not always enough to specify some reasonable constraints and synchronization mechanisms to get an (optimal) working FPGA circuit.

So I'd like to know if there are suggestions or examples concerning say extra IO registers to the FPGA, but preferably
something of a set of rules fo successful blueprints, for all I care to add a whole custom processor in the FPGA.

Any potentially relevant comments welcome.

T.V.

[tnt]

In Zynq, the standard way to connect new PL (programmable logic) cores to the PS (programmable system = ARM), is to use the AXI4 interface.

[hewsmike]

[mark03]

The Zynq 7020 is the whole reason I pre-ordered my Parallella. Nothing against the Epiphany, I'm sure it's interesting, but Parallella was (and AFAIK still is) by far the most cost-effective Zynq dev board. So I hope we can get a community of folks figuring out how to add logic in the Zynq. The thermal issues are worrying; I hope they get sorted out.

FWIW, the last time I looked at this, the Vivado software was the major bottleneck. The ZedBoard people have some walk-throughs for adding PL, and the only method really sanctioned by Xilinx leans heavily on the various graphical abstractions and wizards in Vivado. The problem is (was?), it is still buggy, so a lot of people were advising to wait for the next release. I believe that is out now. So once the ZedBoard experts update their tutorials, AFAIK those instructions should be fairly applicable to Parallella.

My other problem is that I am new to FPGAs and Verilog, and looking through the code in Adapteva's github repository I can't seem to find any Verilog that actually "does" anything. There are lots of definitions and constraints and macros and connecting of one thing to another, but I haven't found the bit that actually implements HDMI. Maybe that's because it's all graphical through Vivado, using some off-the-shelf component?

[tnt]

The thermal stuff might get a bit better with production Zynq 7020 vs the ES (engineering sample) version that's on the kickstarter version, but I wouldn't expect all that much. FPGA burn power, lots of it. Looks at the zedboard, it has a pretty big heatsink on the FPGA ...

The build instruction for the FPGA bitstream published by adapteva 6 month ago relied on ISE 14.4 and not the Vivado suite. I'll probably try rebuilding a minimal version of adapteva's code (i.e. the e-link only, no hdmi) with vivado 2013.4 in the coming days.

The HDMI code is not part of adapteva's codebase, it comes from an ADI reference design.

[mark03]

[tnt]

[theover]

We all know the clocks of the FPGA are buffered to be usable all over the chip, and there are directives both in some interface commands of VHDL and in Verilog to specify "bottleneck" conditions such that whatever peripheral logic connects with the logic on the FPGA, as defined by the HDL, gets the proper signal/clock timing relations, handshake processes, etc.

However, when making a bit of a design in the FPGA, it is also needed to make sure the parts of the logic design connect up such as the logic designer has intended. For instance for a processor design, you'll want to know that with every possible skew of control signals, the instruction with the longest ("critical") path will still run given the clock speed at hand.

When connecting parts of a logic diagram with state machines in them, you want to know that the setup and hold times of the connecting state machines are such that under no circumstance there is a chance for errornous results, given certain clock speed, and this can depend on "random" constellations of logic defined in the HDL coming out to certain particular slice constellations on the FPGA, and when there are a lot of cross connections, it is possible you have to test the circuit because the HDlanguage constraints cannot necessarily be trusted to be executed right.

Of course there's the electronics level, where it is probably a matter of the maker of the FPGA programming software chain that the available slices ("cells") are connected and fed with supply current in such a way that the circuit will work right (sometimes the router of the Xilinx web-pack makes interesting (seemingly useless "loops' with signals, which can be seen from the graphical connection patters).

I short: making a complicated new design with a HDL requires certain unwritten rules to make the Silicon Compilation come out right, and I'm interested in those rules, as one of my major interests in the Parallella board!

T.

[tnt]

The tool will work out all of that setup/hold stuff for you as long as you use synchronous logic. If will check that every FF -> logic -> FF path meets the setup/hold time requirement while taking into account jitter / skew / temperature / propagation delays etc ...

[Greg Zuro]