Access to hardware of Epiphany Coprocessor

[nizarsd]

Hi,
I'm working on a project for many core fault tolerant design. We'll need to inject faults and test many core system algorithms that tolerate the faults and reconfigure the cores accordingly. I wonder if Parallella is a good platform for me. Mainly, what level of access to hardware configuration is available for Epiphany. Can we migrate tasks between the core at runtime? is there a possibility to shut down some cores when required or change the memory map of the core dynamically ?
Also, I wanted to check if Parallella boards with 64 cores are yet available.
Thank you,
Nizar