Maximum Theoretical Data Bandwidth.

Any technical questions about the Epiphany chip and Parallella HW Platform.

Moderator: aolofsson

Maximum Theoretical Data Bandwidth.

Postby keithsloan52 » Fri Mar 07, 2014 9:31 am

Apologies if this is covered in documentation somewhere, but what is the theoretical maximum bandwidth of communicating data between the Arm processors and the Epiphany Cores. i.e. If the cores did no calculation just passed data back and forth.

Read item in the APL section about implementing pipes and would like to get some handle on what the maximum data throughput might be.
keithsloan52
 
Posts: 17
Joined: Fri Mar 07, 2014 9:22 am

Re: Maximum Theoretical Data Bandwidth.

Postby aolofsson » Fri Mar 07, 2014 9:39 pm

There are a few answers to this question, but here are a few quidelines:

-bandwidth from ARM-->Epiphany (1GB/s possible based on zynq device)
-bandwidth from Epiphany-->ARM (0.6GB/s at 600MHz core clock)
-above bandwidth is duplex and independent of each other
-these bandwidth numbers assume a sequential stream of 64bit writes (eg. addr addr, addr+8, addr+16, addr+24, etc)
-any mix of transactions that doesn't fit the bullet above causes bw to to 1/3
-we are still working on optimizing the FPGA logic (so current bandwidth is less)

Andreas
User avatar
aolofsson
 
Posts: 1005
Joined: Tue Dec 11, 2012 6:59 pm
Location: Lexington, Massachusetts,USA


Return to Epiphany and Parallella Q & A

Who is online

Users browsing this forum: No registered users and 13 guests

cron