Epiphany Module for OpenCV

Epiphany Module for OpenCV

Postby Gravis » Fri Aug 09, 2013 12:28 pm

OpenCV is a great computer vision library and they have created a module to use GPUs. I think it would be great if someone could take that code and modify it to use the Epiphany on the Parallella.

Anyone interested in porting the GPU code?
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Re: Epiphany Module for OpenCV

Postby 8l » Thu Aug 29, 2013 11:33 pm

there is some pdf about zynq and opencv.
http://www.xilinx.com/support/documenta ... pp1167.pdf

XAPP1167 (v2.0) August 27, 2013

This application note describes how the OpenCV library can be used to develop computer
vision applications on Zynq®-7000 All Programmable SoCs. OpenCV can be used at many
different points in the design process, from algorithm prototyping to in-system execution.
OpenCV code can also migrate to synthesizable C++ code using video libraries that are
delivered with Vivado® High-Level Synthesis (HLS). When integrated into a Zynq SoC design,
the synthesized blocks enable high resolution and frame rate computer vision algorithms to be
implemented
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Re: Epiphany Module for OpenCV

Postby Gravis » Fri Aug 30, 2013 1:39 am

8l wrote:there is some pdf about zynq and opencv.

that's nice an all but the zynq isnt the target, it's the epiphany that is the target.
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Re: Epiphany Module for OpenCV

Postby nizar » Thu Dec 19, 2013 12:19 pm

hi there,

this very nice to port opencv to adapteva, probably if this works will be the lowest cost solution,
but there're some technical issue I'd like any body could answer to me:
as we know each EPII processor has 32kb shared memory and I dont think this enough to analyse image frames, is it possible to extend this shared memory by re-adressing it to external DRAM of Zynq ?
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Re: Epiphany Module for OpenCV

Postby 9600 » Thu Dec 19, 2013 1:15 pm

Hi Nizar,

nizar wrote:as we know each EPII processor has 32kb shared memory and I dont think this enough to analyse image frames, is it possible to extend this shared memory by re-adressing it to external DRAM of Zynq ?


It is possible to use external DRAM but access is much slower. If you search the forums you will find previous discussions on this matter.

Details of an example project using OpenCV with Epiphany for face detection can be found in an Adapteva white paper, which includes a link to the source code.

Cheers,

Andrew
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Re: Epiphany Module for OpenCV

Postby nizar » Thu Dec 19, 2013 2:02 pm

Hi Andrew,

thank you very much for your reply,
for my project right now important is computing, we knew the elink has 2gb/s for each direction in single core.
as i'm going to split data process between many chip, at the first step this enough for me even slower until adapteva try to make something similair or more better like TileraPro64 , they has dedicated DDR 4 of them this reduce time to access for SRAM.
But andrew if possible I have a question I'm going to use 64 chipset in single board, and going to use 4 elink port (e,w,n,s)
as we know it has 4bits for col and 4 bits for rows, could u sugguest the best way to orgonize this chipset, my solution right now going to use as follow

4X4 in single board, and 4x16 boards.

to avoid latency of frame analyse I decide to use arbitrer processor quadcore is like imaging co processor,
and all chipset going to be use like 3D matrix multi, 2D, to calculate distance, object size all in rela time.

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Re: Epiphany Module for OpenCV

Postby fdeutschmann » Thu Dec 19, 2013 4:14 pm

nizar wrote:for my project right now important is computing, we knew the elink has 2gb/s for each direction in single core.
as i'm going to split data process between many chip, at the first step this enough for me even slower until adapteva try to make something similair or more better like TileraPro64 , they has dedicated DDR 4 of them this reduce time to access for SRAM.

The Tilera approach is only indirectly comparable to Adapteva's; the Adapteva is a somewhat different approach to the multicore connection / networking problem. The eLink runs plenty fast (300 MHz, 8 bits wide, independent full-duplex links), but the multi-hop aspect leads to the latency issue. This is not necessarily bad, but does have to be contemplated for its consequences on algorithm selection and implementation.

But andrew if possible I have a question I'm going to use 64 chipset in single board, and going to use 4 elink port (e,w,n,s)
as we know it has 4bits for col and 4 bits for rows, could u sugguest the best way to orgonize this chipset, my solution right now going to use as follow

4X4 in single board, and 4x16 boards.

to avoid latency of frame analyse I decide to use arbitrer processor quadcore is like imaging co processor,
and all chipset going to be use like 3D matrix multi, 2D, to calculate distance, object size all in rela time.


With all due respect, sounds like you need to find a partner who has significant hardware design and implementation experience with the signal types involved here. Routing the eLink between Adapteva packages is not too difficult, but connecting it to anything else - whether FPGA or board interconnect - requires very careful PCB design and fabrication given the signals involved. Careful study of the Parallella board Gerbers and the schematic is strongly advised, to get an idea of what is required for working with these chips. Failure to implement this properly will lead to expensive failure!

-frank
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Re: Epiphany Module for OpenCV

Postby nizar » Thu Dec 19, 2013 8:36 pm

hi frank ,
thank you for your reply
I already start doign the design, after doing deep read from pdf manual , we could do settings from ROWS and cols pins, about PCB design I dont have any issue this my area of expertise, but the weired thing, is wich function in SDK could direct a task e.g:
I have 16 chipsets orgonized 4x4, and you know each chipset has 16 cores inside,
I want run main1.c in chipset (1,4) core (0,1) and main5.c to chipset(1,2) core (3,3).
if you could help wich function in SDK that I could check chipset address ?
best regards
Nizar
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