32-bit immediates + hardware looping ...

32-bit immediates + hardware looping ...

Postby hewsmike » Thu Oct 17, 2013 5:04 am

Quick reality checks, if you will.

(A) Constructs like :

MOV R0, %low(90000000);
MOVT R0, %high(90000000);

are because you don't have 32 bit immediates in the opcodes ( so you rely on assembly time breakup of same and do two 16-bit loads ) ?

(B) Apropos of that I've just discovered the hardware loop facility. Neat ! You could phrase just about any variation of for-loop into that ..... :-)

However : is it subject to any 'branch taken penalty' at loop endpoint for non-ultimate iterations ? ( ie. at PC = LE just a straight load of PC = LS on LC > 0 with no fuss )

FWIW ( curiosity ): any especial design reason(s) for the double word boundaries, the 32-bit instruction sizes, minimum of 8 instructions in the loop block, and interrupt disabling ??

Cheers, Mike
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Re: 32-bit immediates + hardware looping ...

Postby timpart » Thu Oct 17, 2013 8:11 am

hewsmike wrote:MOV R0, %low(90000000);
MOVT R0, %high(90000000);

are because you don't have 32 bit immediates in the opcodes ( so you rely on assembly time breakup of same and do two 16-bit loads ) ?

Yes the instructions are all 16 or 32 bits wide so there is no room to fit an opcode and 32 bits of data into one of them. There is a diagram at the end of the architecture manual showing the bit patterns of the instructions.

hewsmike wrote:(B) Apropos of that I've just discovered the hardware loop facility.

However : is it subject to any 'branch taken penalty' at loop endpoint for non-ultimate iterations ? ( ie. at PC = LE just a straight load of PC = LS on LC > 0 with no fuss )

FWIW ( curiosity ): any especial design reason(s) for the double word boundaries, the 32-bit instruction sizes, minimum of 8 instructions in the loop block, and interrupt disabling ??


There is no branch penalty at the end of the loop, the CPU fetches the start of the loop in time to make it seamless. In order to achieve this minor miracle there are many restrictions about the code. More discussion here.

Tim
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Re: 32-bit immediates + hardware looping ...

Postby hewsmike » Thu Oct 17, 2013 10:40 pm

Yes the instructions are all 16 or 32 bits wide so there is no room to fit an opcode and 32 bits of data into one of them. There is a diagram at the end of the architecture manual showing the bit patterns of the instructions.

Of course. My bad. :-)

There is no branch penalty at the end of the loop, the CPU fetches the start of the loop in time to make it seamless. In order to achieve this minor miracle there are many restrictions about the code. More discussion here.

Thanks for that link ! :-)

Cheers, Mike.
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