FPGA and Linux build environment for Parallella

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FPGA and Linux build environment for Parallella

Postby peteasa » Tue Sep 01, 2015 8:06 pm

Hi all,

I just wanted to make you aware that build environment that I have published on Github now has a Getting Started guide at https://github.com/peteasa/parallella/wiki/Getting-started

The environment has a working FPGA bitstream with elink redesign and HDMI connection plus the necessary kernel and linux environment.

Enjoy!

Peter.
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Re: FPGA and Linux build environment for Parallella

Postby tif » Fri Oct 16, 2015 3:56 am

Hi Peter.

Thanks a lot for your tutorial.

I finally managed to get Vivado 2014.4 not only installed but also licensed under Ubuntu.
The main instruction came from http://billauer.co.il/blog/2015/01/vivado-license-activation-ubuntu-linux/. In addition I had to strace the xlicclientmgr and use ldd /opt/Xilinx/Vivado/2014.4/bin/unwrapped/lnx64.o/vivado to see which paths are missing to get all the libraries.

If I use your make according to your tutorial it exits with the below errors:
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ERROR: [BD 41-50] Could not find an IP with the given vlnv: analog.com:user:axi_clkgen:1.0
ERROR: [BD 41-595] Failed to add ip repository block <axi_clkgen_0>
ERROR: [BD 41-425] Failed to read Diagram <elink2_top> from BD file <./7020_hdmi/7020_hdmi.srcs/sources_1/bd/elink2_top/elink2_top.bd>
ERROR: [Common 17-39] 'open_bd_design' failed due to earlier errors.


When I open the 7020_hdmi.xpr I get
Code: Select all
Vivado Commandsgenerate_target all [get_files  /~/Job/peteasa/parallella/parallella-fpga/7020_hdmi/7020_hdmi.srcs/sources_1/bd/elink2_top/elink2_top.bd]
[BD 41-5] processing_system7_0 does not have a bus interface called S_AXI_HP1
[BD 41-5] processing_system7_0 does not have a bus interface called M_AXI_GP1
[BD 41-5] processing_system7_0 does not have a bus interface called IIC_0
[BD 41-5] processing_system7_0 does not have a bus interface called DMA0_REQ
[BD 41-5] processing_system7_0 does not have a bus interface called S_AXI_HP0
[BD 41-5] processing_system7_0 does not have a bus interface called DMA0_ACK
[BD 41-6] processing_system7_0 does not have a port called M_AXI_GP1_ACLK
[BD 41-6] processing_system7_0 does not have a port called S_AXI_HP1_ACLK
[BD 41-6] processing_system7_0 does not have a port called S_AXI_HP0_ACLK
[BD 41-6] processing_system7_0 does not have a port called DMA0_ACLK
[BD 41-6] processing_system7_0 does not have a port called GPIO_I
[BD 41-6] processing_system7_0 does not have a port called GPIO_O
[BD 41-6] processing_system7_0 does not have a port called GPIO_T
[BD 41-6] xlconcat_0 does not have a port called In15
[BD 41-6] processing_system7_0 does not have a port called IRQ_F2P
[BD 41-6] xlconcat_0 does not have a port called In14
[BD 41-6] processing_system7_0 does not have a port called FCLK_CLK2
[BD 41-6] xlconcat_0 does not have a port called In2
[BD 41-6] xlconcat_0 does not have a port called In3
[BD 41-6] xlconcat_0 does not have a port called In4
[BD 41-6] xlconcat_0 does not have a port called In5
[BD 41-6] xlconcat_0 does not have a port called In6
[BD 41-6] xlconcat_0 does not have a port called In7
[BD 41-6] xlconcat_0 does not have a port called In8
[BD 41-6] xlconcat_0 does not have a port called In9
[BD 41-6] xlconcat_0 does not have a port called In10
[BD 41-6] xlconcat_0 does not have a port called In11
[BD 41-6] xlconcat_0 does not have a port called In12
[BD 41-6] xlconcat_0 does not have a port called In13
[BD 41-50] Could not find an IP with the given vlnv: analog.com:user:axi_clkgen:1.0
[BD 41-595] Failed to add ip repository block <axi_clkgen_0>
[BD 41-425] Failed to read Diagram <elink2_top> from BD file <~/Job/peteasa/parallella/parallella-fpga/7020_hdmi/7020_hdmi.srcs/sources_1/bd/elink2_top/elink2_top.bd>
[BD 41-82] Exec TCL: no open design
[BD 41-1031] Hdl Generation failed for the IP Integrator design ~/Job/peteasa/parallella/parallella-fpga/7020_hdmi/7020_hdmi.srcs/sources_1/bd/elink2_top/elink2_top.bd
[BD 41-71] Exec TCL: Cannot find design elink2_top


I'm currently trying to figure out why.
tif
 
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Re: FPGA and Linux build environment for Parallella

Postby peteasa » Fri Oct 16, 2015 3:13 pm

Your errors seem to indicate that the Analog Devices Inc cores have not been built, there is a Makefile in AdiHDLLib (https://github.com/peteasa/parallella-f ... b/Makefile) that should have been called up from the top level Makefile and will build these. It is possible that you did not update to the latest version of the project.. before you start navigate to the top level folder (parallella) and try
Code: Select all
git fetch --all

to see if any new stuff is available and if so try
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git pull
source ./updatesubmodules.sh


In my work I was aiming at getting the hdmi Analog Devices Inc cores working so I followed the library requirements for them and used Vivado 2014.4.1. The 2014.4.1 patch can only be applied if you have installed at least the Design Suite version then you can install the 2014.4.1 patch. You end up with a licensed version of vivado that will expire after 30 days, but you still can use the product and build the fpga. Having said that it would also be possible to use 2014.4 version however to use that you would need to modify the file AdiHDLLib/library/scripts/adi_ip.tcl and AdiHDLLib/projects/scripts/adi_project.tcl files and replace 2014.4.1 with 2014.4. After building the Analog Devices Inc cores the folder AdiHDLLib/libarary/axi_clkgen, axi_hdmi_tx, axi_spdif_tx contain the necessary cores.

The second set of errors look more serious, almost as if the Vivado libraries are not completely installed. You seem to have had more problems installing Vivado that I did.. I tend to download the whole 5G tar.gz file then the unzip and install is relatively painless until you get to the bit where the license file has to be generated. Typically this does not pull up necessary web page - http://forums.xilinx.com/t5/Installatio ... d-p/454830
If you grab a .lic file by accident, the license manager won't let you grab a .xml on the same "request". Unfortunately, the tool's default (vlm and xlicclientmgr) is to reuse the existing request, which is endlessly frustrating. The solution is to force xlicclientmgr to create a new request. I did it like so:
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xlicclientmgr -cr request.xml reference="Some_unique_name"

This produces an html file with a brand new "request", which you can open in a browser and follow the prompts to get a Vivado license.xml file, avoiding the messed up one. What you end up with is a working system that does not need the flex license manager that you seem to have ended up with.

Anyway by Dec 2015 Analog Devices Inc will release the updated libraries that will work with Vivado 2015.2 and as far as I can tell the WebPACK version will be ok for that. So plan to update later this year to the 2015.2 version.
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Re: FPGA and Linux build environment for Parallella

Postby tif » Tue Oct 20, 2015 4:54 am

My problem with the licensing part was either because I had tried to install different ISE and Vivado versions before, or because my Ethernet adapter was on eth2 and none on eth0. I did the whole procedure from the provided link and finally it worked. It bugged me before when other software had over-complicated licensing procedures for free or trial versions (Quartus is no exception) but Xilinx so far is top on the aggravation scale.

The bash script updatemodules.sh worked with the edit of line 29 from
Code: Select all
if [ $0 != "bash" ]; then
to
if [ `basename "$0"` != "bash" ]; then

and saving it a level higher (cd parallella added to the second line), so that git does not complain about locally modified files.

I tried with your suggestions to change the tcl-scripts but finally had to update to 2014.4.1 as other libraries failed with the 2014.4 version.

Makefile completed. I ignored a row of warnings and hoped that it will still produce the intended result.

Code: Select all
Adding component instance block -- adapteva.com:Adapteva:parallella_gpio_emio:1.0 - parallella_gpio_emio_0
WARNING: [BD 41-434] Could not find an IP with XCI file by name: elink2_top_parallella_gpio_emio_0_0
Adding component instance block -- adapteva.com:Adapteva:parallella_i2c:1.0 - parallella_i2c_0
WARNING: [BD 41-434] Could not find an IP with XCI file by name: elink2_top_parallella_i2c_0_0
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_0
WARNING: [BD 41-434] Could not find an IP with XCI file by name: elink2_top_proc_sys_reset_0_0
[snip]


After that I opened the 7010_hdmi.xpr in Vivado (opened with zero error messages!) and started the synthesis. Here I got the two warnings I already know dearly from the run of other versions:
Code: Select all
[BD 41-237] Bus Interface property MASTER_TYPE does not match between /elink2/eCfg_0/mi(OTHER) and /elink2/axi_bram_ctrl_2/BRAM_PORTA(BRAM_CTRL)
There are three different solutions on the Internet how to fix this but I am still trying to make one of them work. Apart from this the run was successful.

Implementation displayed the resulting error from the two above in synthesis:
Code: Select all
[Memdata 28-122] data2mem failed with a parsing error. Check the bmm file or the bmm_info_* properties on the BRAM components. The design BRAM components initialization strings have not been updated.

The bitstream generation resulted in a 2 MB file.

As my version contains the Zynq7020 I opened the 7020_hdmi/7020_hdmi.xpr next. This version unfortunately gives me errors on startup:
Code: Select all
 [Synth 8-439] module 'elink2_top' not found ["/home/user/peteasa/parallella/parallella-fpga/7020_hdmi/7020_hdmi.srcs/sources_1/bd/elink2_top/hdl/elink2_top_wrapper.v":180]
[Synth 8-285] failed synthesizing module 'elink2_top_wrapper' ["/home/user/peteasa/parallella/parallella-fpga/7020_hdmi/7020_hdmi.srcs/sources_1/bd/elink2_top/hdl/elink2_top_wrapper.v":12]
[Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details

[BD 41-703] Peripheral </elink2/esaxi_0/S00_AXI/S00_AXI_mem> is mapped into master segment </processing_system7_0/Data/SEG_esaxi_0_S00_AXI_mem>, but there is no path between them. This is usually because an interconnect between the master and the peripheral has become misconfigured. Check and reconfigure the interconnect, or delete the master segment.
 [BD 41-1031] Hdl Generation failed for the IP Integrator design /home/user/peteasa/parallella/parallella-fpga/7020_hdmi/7020_hdmi.srcs/sources_1/bd/elink2_top/elink2_top.bd
 [BD 41-703] Peripheral </elink2/esaxi_0/S00_AXI/S00_AXI_mem> is mapped into master segment </processing_system7_0/Data/SEG_esaxi_0_S00_AXI_mem>, but there is no path between them. This is usually because an interconnect between the master and the peripheral has become misconfigured. Check and reconfigure the interconnect, or delete the master segment.
 [BD 41-1031] Hdl Generation failed for the IP Integrator design /home/user/peteasa/parallella/parallella-fpga/7020_hdmi/7020_hdmi.srcs/sources_1/bd/elink2_top/elink2_top.bd


In parallel I found that the files out of the parallella_7020_headless.xpr.zip archive built with little additional effort. I had to update the IPs for whatever technical reason, leaving me with the above BRAM_CTRL error. Apart from this everything down to generating the bitstream went smoothly. Only thing is, the bin file has 3.9 MB whereas the original file has only 2 MB. My custom Verilog code did not show any function even though I made sure that the part was not going bush due to optimisations. So I guess my BIN file is getting rejected or misinterpreted.
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Re: FPGA and Linux build environment for Parallella

Postby peteasa » Tue Oct 20, 2015 8:07 pm

Thanks for your comments on the shell script I have made some changes that might make it work a bit better next time!

I have two un-archive tcl scripts one for the xc7z020clg400-1 and the other for the xc7z010clg400-1 project. My Makefile attempts to run both of these to create the two 7020_hdmi.xpr and 7010_hdmi.xpr projects. The first set of warnings that you show are informational and after the run you should find the elink2_top_parallella_gpio_emio_0_0.xci, elink2_top_parallella_i2c_0_0.xci and elink2_top_proc_sys_reset_0_0.xci files in the appropriate folder within 7020_hdmi/7020_hdmi.srcs/sources_1/bd/elink2_top/ip. I guess the warning logs are telling you that the .xci files are being created.

The bmm file error is not an important error for this project. I understand (http://www.xilinx.com/support/documenta ... ta2mem.pdf) that the bmm file is used by the Data2MEM tool to combine software (ELF) file and memory description into the fpga bitstream so that you can insert ELF or DRF files into the bitstream and run the CPU from instructions in the fpga memory. In this design the memory is internal to the elink2 block and there is no need to load and ELF file into the bitstream. Indeed I have seen other posts on the xilinx forum that show how to suppress the running of the tools that generate the errors!

The last set of errors you report seem to indicate that the Output Products have not correctly generated. You can try to do this by hand if you open the 7020_hdmi.xpr project in vivado then in the {Project Manager - 7020_hdmi; Sources; Hierarchy} view you can expand the "Design Sources" group and you will see elink2_top_wrapper (elink2_top_wrapper.v). Double click on "elink2_top_wrapper" to navigate to elink2_top_i - elink2_top (elink2_top.bd) and right hand mouse click on this to get a menu. About the 5th down on the list is "Generate Output Products..." .. have a go with that and it should create the missing bits. Once done you should be able to navigate into elink2_top_i to see elink2_top (elink2_top.v) and of course the associated file will have appeared in the filesystem at 7020_hdmi/7020_hdmi.srcs/sources_1/bd/elink2_top/hdl/elink2_top.v. One thought is that in the un-archive scripts I found that I had to correct the axi_interconnect_0 blocks that when generated seemed to get default AXI master /slave bus configuration of 1 AXI slave bus in and 2 AXI master busses out. The axi_interconnect_0 block on the top level should have 1:5 AXI busses and the second one in the hdmi block should have 1:1 AXI bus. This is easy to fix if you navigate to the {Flow Navigator; IP Integrator} section and click on "Open Block Design" -> elink2_top.bd you can then select the top level axi_interconnect_0 with the right hand mouse button and run the "Customize Block..." to check / correct the configuration so that it has 1 Slave and 5 Master interfaces. The second axi_interconnect_0 is within the hdmi block so you have to double left mouse click on that block to see it. Again use the "Customize Block..." to check / correct the configuration.

Finally double check that the Address Editor (it shows up on a tab next to the block design Diagram) shows the Offset Addresses are all correctly assigned and that there is no block without an Offset Address... The master information for that is in https://github.com/peteasa/parallella-f ... nk2_top.bd .. you will see the address information on line 4010 in the
Code: Select all
<spirit:library>Addressing/processing_system7_0</spirit:library>
block for example HDMI_0/axi_vdma_0 is at 0x43000000.

Peter
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Re: FPGA and Linux build environment for Parallella

Postby tif » Wed Oct 21, 2015 7:10 am

Generate output products produced the error
[BD 41-703] Peripheral </elink2/esaxi_0/S00_AXI/S00_AXI_mem> is mapped into master segment </processing_system7_0/Data/SEG_esaxi_0_S00_AXI_mem>, but there is no path between them. This is usually because an interconnect between the master and the peripheral has become misconfigured. Check and reconfigure the interconnect, or delete the master segment.

In the top of the Diagram window appeared a "Designer Assistance available. Run connection automation". It offers to connect two signals: axi_protocol_converter_0/M_AXI and HDMI0/M00_AXI.
I tried it and reverted it because it did not help.

So I opened the 7010_hdmi.xpr on the Win7 VM and reorganised the 7020_hdmi to have all blocks in the same place. The differences are:
HDMI_INT not connected to xlconcat_0
xlconcat has only In0 and In1 instead of In0 to In15.
xlconcat dout is not connected to processing_system7_0, which features no port IRQ_F2P.
There are a lot more missing links, apparently because processing_system7_0 has only 6 busses instead of 27.

I customized the processing_system7_0 IP to get all the required interfaces and connected them by hand. Now I would have to check all the customisation options which are not the same...
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Re: FPGA and Linux build environment for Parallella

Postby peteasa » Wed Oct 21, 2015 7:06 pm

@tif: Not sure what has happened to your environment! Sounds like time to reset. If you look at the git master files you will see that there is very little difference between the 7010 and the 7020 source files (tcl, xpr and elink2_top .bd and wrapper.v files). I would be tempted to clone a new environment and start again with the new environment now that you have become familiar with all the files and potential issues. Go to a new fresh location and type (assuming you are on a 64bit machine with the xilinx tools in /opt/xilinx):
Code: Select all
source /opt/xilinx/Vivado/2014.4/settings64.sh
git clone https://github.com/peteasa/parallella-fpga.git startfromscratch
cd startfromscratch
make all
vivado 7020_hdmi/7020_hdmi.xpr

It should be as simple as that!.. If that produces the same effects then I would not know how to help since I have not seen anything like the problems that you have had. If the 7010 project builds ok then the 7020 project should build just the same.
Hope that works for you!

@CharityDu, @Aldowin - thanks for the comments..

Peter.
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Re: FPGA and Linux build environment for Parallella

Postby peteasa » Sat Nov 21, 2015 6:05 pm

I know its a bit late but I have just found a fault in the 7010 build script. Xilinx insist on using full path names in the generated files. I tend to try to remove as many of these as possible and whilst doing other work I spotted that I had missed a full path to a file that would not exist on any machine apart from my machine. So I have now fixed that.
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Re: FPGA and Linux build environment for Parallella

Postby Kalicutt » Tue Dec 15, 2015 6:34 pm

Your guide has been a huge help to me getting started developing for my own custom application of the Parallella, which requires modification of FPGA, devicetree, Linux kernel, and software run on the device.

I have a few questions after having worked with the guide for a while:
1) I would like to base my work off of the current HDMI Embedded version of the image on the parallella website quickstart guide. This has the root file system, bitstream, devicetree, and kernel all separately compiled and working with the Parallella. It is possible to take a custom bitstream, created through customizing your Vivado HDMI project, and add it directly to the SD card's boot partition. However, in my case I also need to modify the device tree and linux kernel to add support for new devices. Changing the bitstream works fine, changing the device tree works fine, but when it comes to changing the kernel, I am not able to create a bootable image (or at least the Ethernet is not working not allowing me to access the device, since the HDMI never works). I notice you mention you are using the analogdeviceinc linux kernel version 3.19 branch 2015_R1. Is it possible to either directly or from within the yocto system provide the configuration used for the kernel? I have tried some of the default zynq configs, along with the parallella_defconfig in the parallella kernel repo, and nothing has worked so far.

2) Is it true that the headless version of the Parallella, without HDMI, does not have a stable Vivado project? I have seen evidence of this elsewhere but would like a direct confirmation.

3) The yocto building method is a lengthy process, is there a way to not have to remake the root file system? I am only interested in the device tree, bitstream, and kernel image.
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Re: FPGA and Linux build environment for Parallella

Postby peteasa » Tue Dec 15, 2015 10:47 pm

The quick answer is yocto for everything or choose something else! If you just want to build the kernel why not build it on the parallella? There are posts about building the kernel on its own.. basically the process would be to get a working image with the matching kernel source, get the .config that was used to build the kernel from the environment then build the kernel source with that config and install that. Install that version of the kernel check it works then make your changes to the kernel driver source and rebuild. Have a look at viewtopic.php?f=48&t=1230 to start with. The trick would be to start with a distribution that has the matching kernel source.

I moved to the ADI kernel because I needed the hdmi drivers for the ADI fpga modules and it seemed to be easiest to patch in the couple of files needed to get the epiphany driver going than struggle to back port ADI kernel stuff to an older kernel. Since then I have been extending the epiphany driver and am using the latest oh fpga and it all still works quite well. Dont forget that yocto also gives you a full gui interface if you want so you dont just have to stick with the command line!

The headless Parallella does have a working Vivado project.. its in a zip file on the parallella-hw see https://github.com/parallella/parallell ... o/releases. What you have to do when mixing and matching is ensure that the get the correct matching epiphany sdk. That is what I try to present with my github parallella project.. the elink-redesign default branch uses the commit SRCREV = "be28d22caf3e09aa5813ec3a946279af2ee5191c" see https://github.com/peteasa/meta-epiphan ... dk_1.0.inc that works with this zip file! So you would build your kernel then build that version of the epiphany-sdk, build your fpga project based on that zip file and it would all work and you could use the epiphany chip.

Ok so if you must just build the bits that you need with yocto.. this is how I do it: bitbake -c cleansstate virtual/kernel will clean the kernel, bitbake hdmi-image-debug will build everything but if its already been built it will just build the kernel and put it in the deploy folder. Same thing with the device tree and the bitstream so bitbake -c cleansstate parallella-hdmi-bitstream and bitbake -c cleansstate device-tree will do what you want. Now you want to fix up the kernel and the device tree with your own bits.. create an bbappend recipe and override the SRCREV and the SRC_URI and you can pull in your own local git bare repository with whatever you want (SRC_URI = "git:///home/peter/Projects/parallella/parallella-hw-peter.git") for example... Or you can patch the kernel on the go... bitbake -c cleansstate virtual/kernel will clean the kernel, bitbake -c configure virtual/kernel will pull in the kernel and patch it.. then you can add your own patches then bitbake hdmi-image-debug to build. It does not build the rootfs because it does not know that you have done some manual patching. Anyway by the time it starts doing the rootfs the bits you want are already in the deploy folder so you dont even have to wait if the rootfs is being built you can just pick what you need and copy to the sd card. I still think that the neatest solution would be to build the kernel and the device tree on the parallella for what you want to do.. but anything is possible!
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