FPGA and Linux build environment for Parallella

[Kalicutt]

Thanks for the reply.

I have tried various configuration and guides, including the one you mention, using both a cross compiler and using the parallella itself. Unfortunately whenever I take a kernel and make my own uImage, the Ethernet on the Parallella does not function, not allowing me to get a handle on what is wrong as the HDMI does not work on our Parallella. That is the reason I have turned to the Yocto alternative. I am pleased to say I compiled the project and my Parallella booted up fine with the device tree, kernel, and bitstream, then added my own custom bitstream, device tree, and added configuration modules to the kernel inside Yocto, and things are working great! I think I will be sticking with this route due to the flexibility it provides.

As for the headless .xpr project, I have loaded it into Vivado, in the version they state (2014.2) and it ran into problems with synthesis failing. Have you run into this? Did the HDMI version initially have the same issue before modifying it?

[peteasa]

difficult to say if the errors / warnings I see are the same as yours unless you detail the errors / warnings that you are seeing! Some errors are expected and can be ignored.. best thing is to generate a bit.bin and try it out ignoring any errors / warnings in the build process! Some of the errors that I see are documented in this discussion thread, for example the bmm file error.. so have a look and if there is something new post the errors / warnings that you are getting.

[Kalicutt]

Has this Vivado project for the 7020 Zynq been used to generate an FSBL in SDK and used to flash the parallella through JTAG? I need to change the boot procedure to accomodate voltage level shifting for the PS SPI module routed to EMIO, but would like to know before trying as I do not want to brick a Parallella.

[peteasa]

I have not yet reflashed the fsbl. Tried to avoid reflash of fsbl till I am forced into doing it.

[peteasa]

Added a brief tutorial and some helper scripts to help with Verilator simulation of the oh design. Have a look at https://github.com/peteasa/parallella/w ... -waveforms for a quick overview of the GTKWave scripts that I use to display significant parts of the oh design if you are interested.

[aolofsson]

That is very cool. I hadn't tried Verilator yet, because I didn't think it would run through the delay statements in PLL code. Did you have to do something special to get it to run?
(my experience with Verilator is a little stale..things might have changed in the last few years)

[peteasa]

Good point.. not so cool! I have not yet got Verilator running.. Updated the wiki https://github.com/peteasa/parallella/w ... h-IVerilog

[peteasa]

[cmcconnell]

[peteasa]

Just thought I would let anyone interested know that the environment is now updated with linux 4.4 kernel, oh fpga, adi kernel drivers, hdmi and sound working.