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Creating an FPGA accelerator in 15 minutes

PostPosted: Thu Jan 21, 2016 8:50 pm
by aolofsson
I finally got around to creating an FPGA "sandbox" example for parallella.

Completely scripted. As long as you have Vivado installed, just edit the verilog code and build with one command. No dependency on Xilinx proprietary IP generator. No need to open the GUI. ... 5-minutes/

Re: Creating an FPGA accelerator in 15 minutes

PostPosted: Mon Jan 25, 2016 11:02 pm
by theover
I've downloaded the git project, ran the supplied commands after correcting the first "cd" command, and after a minute or so, there were errors in the build. Also, I understand this project makes use of the constructs usually used for the Epiphany chip, but is there an example how to address the resulting accelerator from C/Linux, and if so, is that instead of the Epiphany or, in addition to ?


Re: Creating an FPGA accelerator in 15 minutes

PostPosted: Mon Jan 25, 2016 11:19 pm
by aolofsson
-please report error here or file an issue?

-the software is linux. If youwant to runin user space with /dev/mem you will need to run as sudo.

Re: Creating an FPGA accelerator in 15 minutes

PostPosted: Sun Aug 28, 2016 10:38 am
by Melkhior
aolofsson wrote:-please report error here or file an issue?

Some missing files and vivado is outputing some errors :-(

I have Vivado 2015.2 Webpack with all the options (SDK is needed for bootgen; anything newer didn't work because of IP version issues ?)
If I:
1) go into "oh/src/parallella/fpga/parallella_base" and run ./;
2) go into "oh/src/parallella/fpga/headless_e16_z7010" and run ./
I get a file "parallella_e16_headless_gpiose_7010.bit.bin" that works fine when cat'ed in /dev/xdevcfg or as a replacement /boot/parallella.bit.bin.
So I assume my setup is OK.

However for the accelerator...

1) there is no oh/src/accelerator/dv/ or oh/src/accelerator/dv/;
2) there is no oh/src/accelerator/dv/tests/hello.emf but a test_basic.emf instead;
3) If I go into oh/src/accelerator/fpga and run ./, it finishes with:
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-1223] The version limit for your license is '2015.11' and will expire in -272 days. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
ERROR: [Synth 8-2841] use of undefined macro CFG_ASIC [oh/src/accelerator/fpga/system.srcs/sources_1/ipshared/]
ERROR: [Synth 8-2715] syntax error near ; [oh/src/accelerator/fpga/system.srcs/sources_1/ipshared/]
ERROR: [Synth 8-1031] ASIC is not declared [oh/src/accelerator/fpga/system.srcs/sources_1/ipshared/]
INFO: [Synth 8-2350] module oh_memory_dp ignored due to previous errors [oh/src/accelerator/fpga/system.srcs/sources_1/ipshared/]
Failed to read verilog 'oh/src/accelerator/fpga/system.srcs/sources_1/ipshared/'
INFO: [Common 17-83] Releasing license: Synthesis
7 Infos, 1 Warnings, 0 Critical Warnings and 4 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
INFO: [Common 17-206] Exiting Vivado at Sun Aug 28 12:06:58 2016...
[Sun Aug 28 12:06:59 2016] synth_1 finished
wait_on_run: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:12 . Memory (MB): peak = 1102.562 ; gain = 0.000 ; free physical = 10451 ; free virtual = 12417
## launch_runs impl_1
ERROR: [Common 17-70] Application Exception: Failed to launch run 'impl_1' due to failures in the following run(s):
These failed run(s) need to be reset prior to launching 'impl_1' again.

while executing
"source ../../common/fpga/system_build.tcl"
(file "run.tcl" line 12)
INFO: [Common 17-206] Exiting Vivado at Sun Aug 28 12:06:59 2016...
[ERROR] : Bitstream parsing error !!! Unsupported BIT file
cp: cannot stat `system_wrapper.bit.bin': No such file or directory

So obviously no bistream. Also, it references a Zynq 7020 and I have a Zynq 7010 in my desktop parallella. I don't know how to fix either issue.

Also, if I get it to work, will this new bitstream support the Epiphany chip? That why I'm using this and not the Kirill project. I want to run the parallel bits of the algorithm(s) on the Epiphany and the sequential bits of the FPGA. With the help of the Yanidubin tutorials I manage to make it work a while ago, but that was with the ISE using an older version of the code.

Any help or suggestion appreciated.

Re: Creating an FPGA accelerator in 15 minutes

PostPosted: Wed Aug 31, 2016 6:43 am
by peteasa
Hi @Melkhior,
Not run the sample but I have seen some of the issues.
undefined macro CFG_ASIC

When simulating CFG_ASIC is supplied on the command line see for example scripts/ has -DCFG_ASIC=0
Code: Select all
iverilog -g2005\
 -y .\
 -y $OH_HOME/symlinks/hdl\
 -y $OH_HOME/symlinks/dv\
 -I $OH_HOME/symlinks/hdl\
 -o dut.bin\

When building the bit stream the same thing is done for vivado via tcl scripts see ... ddcfb01128. the key bit is to add the options in system_params.tcl (see ... ms.tcl#L28) as an example, then the common/fpga/system_build.tcl script will pick that up with the command
Code: Select all
set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value $oh_synthesis_options -objects [get_runs synth_1]

That will also fix the other two errors.. should be quite a simple fix for you.

And to redirect to a different zync chip have a look at ... ams.tcl#L9. Just change that line and it should spring into life for you as a 7010 build.

Hope that helps


Re: Creating an FPGA accelerator in 15 minutes

PostPosted: Wed Aug 31, 2016 12:47 pm
by Melkhior
peteasa wrote:the key bit is to add the options in system_params.tcl

In this subdirectory it seems to be "run_params.tcl" instead ? (both exist in the subdirectory, but the "" script uses "run_params.tcl").

Hope that helps

Yes, thank you. I got the bitstream it seems, "parallella.bit.bin".
Unfortunately I won't be able to try the bitstream, as I've stupidly managed to fry my parallella :-(
(apparently, parallellas aren't water-proof...)


Re: Creating an FPGA accelerator in 15 minutes

PostPosted: Thu Sep 06, 2018 1:07 am
by cpantel

I'm new, I had success with many of parallalla examples but now I'm stuck here, a little more than 15 minutes ;-)

I really really liked this computer, just had to say it. Let's continue...

First tried with 2015.2 up to the CFG_ASIC error on a just cloned source

Then used 2015.4 on a clean clone and got the CFG_ASIC as a warning, instructions for upgrading the version and finally another error:

CRITICAL WARNING: [HDL 9-870] Macro <CFG_ASIC> is not defined. [src/oh_memory_dp.v:36]
CRITICAL WARNING: [HDL 9-806] Syntax error near ";". [src/oh_memory_dp.v:36]
CRITICAL WARNING: [HDL 9-806] Syntax error near ";". [src/oh_dsync.v:18]
This script was generated using Vivado <2015.2> and is being run in <2015.4> of Vivado. Please run the script in Vivado <2015.2> then open the design in Vivado <2015.4>. Upgrade the design by running "Tools => Report => Report IP Status...", then run write_bd_tcl to create an updated script.
CRITICAL WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'system' instantiated as 'system_i' [/github/oh_2015.2/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system_wrapper.v:16]
ERROR: [DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'system_i' of type 'system_i/system' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.

I followed the instructions: run 2015.2, open with GUI, report ip status... write_bd_tcl, run 2015.4 and got the same errors.

Any hints?

Attached is the log of the last step:
first 2015.4 run -> no
2015.2 run -> no
GUI -> no
sed -i -e "s/2015.2/2015.4/" \
src/spi/fpga/system_bd.tcl \
src/parallella/fpga/headless_e16_z7010/system_bd.tcl \
src/parallella/fpga/headless_e16_z7020/system_bd.tcl \
src/parallella/fpga/sdr_fmcomms/system_bd.tcl \
src/gpio/fpga/system_bd.tcl \
second 2015.4 run -> YES

Re: Creating an FPGA accelerator in 15 minutes

PostPosted: Thu Sep 27, 2018 2:00 am
by olajep

Use the stable branch of
git clone
cd oh
git checkout stable

cpantel wrote:...
sed -i -e "s/2015.2/2015.4/" \

Are you sure you're not on 2015.4.1 ?
sed -i -e "s/2015.2/2015.4.1/"
might work

When you switch to a newer version of Vivado you need to also need to open the xpr file in Vivado and upgrade IPs. Tools->Upgrade IP IIRC


Re: Creating an FPGA accelerator in 15 minutes

PostPosted: Mon Oct 08, 2018 1:45 am
by cpantel

About the branch:

If I checkout "stable", the landscape changes far beyond my little current knowledge.

Anyway, I will try this way, in a few days (weeks?) I'll tell you.

About the versions:

~/Xilinx/Vivado/2015.2/bin/vivado -version
Vivado v2015.2 (64-bit)
SW Build 1266856 on Fri Jun 26 16:35:25 MDT 2015
IP Build 1264090 on Wed Jun 24 14:22:01 MDT 2015
Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

./Xilinx/Vivado/2015.4/bin/vivado -version
Vivado v2015.4 (64-bit)
SW Build 1412921 on Wed Nov 18 09:44:32 MST 2015
IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015

thank you

Re: Creating an FPGA accelerator in 15 minutes

PostPosted: Thu Oct 18, 2018 10:11 pm
by cpantel

Finally, I closed my eyes and zen picked a commit near master that just worked (258cda9). Then, kind of bisected (70a6f14,2f91330, fbfe559, afccd4a, ee2e234) towards master until the the last working commit (afccd4a).

FAIL CFG_ASIC 2017-04-24 21:57:56 70a6f14 Merge pull request #99 from olajep/zcu102
FAIL CFG_ASIC 2017-02-10 17:00:55 2f91330 common/fpga/create_ip.tcl: Fix error when sub-IP is locked
? 2017-02-09 23:03:51 37a38ab zcu102: zcu102: Use Petalinux 2016.4 design as base
? 2017-02-07 23:02:10 02955c0 zcu102: zcu102: Define oh_verilog_define
FAIL CFG_ASIC 2017-02-07 23:01:50 fbfe559fpga/system_build.tcl: Support oh_verilog_define flag
FAIL CFG_ASIC 2017-02-07 19:11:05 ee2e234 Revert "common/hdl: Fix syntax error when CFG_ASIC is undefined"
OK 2017-02-07 18:47:42 afccd4a zcu102: zcu102: Fix Makefile deps and clean target
? 2017-02-07 18:45:52 8706590 zcu102: zcu102: Remove cclk1 port
OK 2017-02-07 18:44:04 258cda9 fpga/system_build.tcl: Create files for SDK

It seem ok till now.

1) First question:

when I tried the xdevcfg method, it seems to timeout

cat parallella.bit.bin > /dev/xdevcfg
cdns-i2c e0004000.i2c: timeout waiting on completion
cdns-i2c e0004000.i2c: timeout waiting on completion
cdns-i2c e0004000.i2c: timeout waiting on completion

it is normal? I left it two minutes, I do not think so.

2) I burned the bitstream in the BOOT partition, compiled driver.c and test.c ok, but when run, it fails:

f_map: No such file or directory
Segmentation fault

when tries to open /dev/epiphany, that does not exist.

//Open /dev/mem file if not already
if(mem_fd < 1) {
mem_fd = open ("/dev/epiphany", O_RDWR);
if (mem_fd < 1) {
return -1;

I saw viewtopic.php?f=48&t=1528, but it seems to old (2014), it should've failed with the 15 minutes example (2016-2017)

My uname -a:

Linux parallella 4.6.0+ #1 SMP PREEMPT Wed Dec 7 13:27:40 CET 2016 armv7l armv7l armv7l GNU/Linux

Any hints or advice?