Parallella Community

I have now tried with a 47uF tantalum cap between pin 3 and 4.
Out of 10 starts with a 30 sec. pause, there was 10 success.

Frida, your wire mod worked for me. The USB on my 7020 board had never worked before this mod.

Since I have the big heatsink on my board, I connected from CR10 pin1 to the BOARD_RESET_L side of R295 (bottom of the board).

Before making the wire mod, I tried a 10nF ceramic cap between R295 and the ground side of R294, but that did not make a difference for me. I might scrounge up a larger tantalum cap later and see if I can get it working that way. Otherwise, I may try replacing R295 with a 10K or 100K resistor to increase the RC time delay for deasserting the reset. The wire mod is too fragile to be a permanent fix.

Well it has been a while since.
Is there anybody here, that have looked at the logik from the FPGA to the USB.??

Is the "STP" "p0_usb_stp" signal high, until the FPGA has sat up the data lines to the USB, and is ready to talk to the USB.??

I found out, I have a window from ca. 30 ms. to 10sec., where I can held down "BOARD_RESET_L", and still have my USB to work.

When login is reached, I can held "BOARD_RESET_L" low for a minute or so, and when I release it , it all works again.

I hope that somebody with insight in the FPGA will chime in.