USB workaround

Hardware related problems and workarounds

Re: USB workaround

Postby ESI » Sat Sep 06, 2014 9:00 am

Hi there,
I did some digging in the data sheets. In my opinion the problem could be the initialization of the MIO pins for the ULPI.
After reset the MIO-pins for ULPI are configured input with pullup (3.3v).
In 15.16.1 of the Zynq TRM the order of initialization is mentioned, the STP pin is configured last. In the FSBL the STP pin is configured after ULPIDATA(4) and DIR and before of the rest of the pins - I took this information by making an FSBL-from scratch, based on the ps7_system_prj.xml-file. If someone could provide the actual FSBL source (ps7_init.c) I could check again.
The other pins will be configured right after this, but I guess the CPU is not running at full speed, because ARM-PLL and IO-PLL are configured after that. The USB-Controller IPCore (which signals the STP) is not held in reset by default, so I guess the STP could be 0 after configuring the MIO-pin for it. In this case we are signalling the PHY "ok to go" while we are still configuring the rest of the pins, and then configuring (and waiting for lock) the PLL for the core and io.
All while the USB core is not held in reset. My guessing is, that this could be very confusing for the PHY...

Possible solutions (IMHO):
The correct order should be:
USB-IPCore th reset
Confgure MIO-Pins - STP should be last - (to check STP is signalled 1, if USB-IPCore is in reset)
deassert reset after all PLL setting are done
This could be done in two ways:
1. edit FSBL (by hand), to the correct order of initialization
2. deactivate USB from Plattform Studio-project and generate FSBL, so MIO-Pins are not touched by FSBL. The do init in uboot.

sorry for only sharing the info without really doing it, I will try to do it, if I find time,
meanwhile, if someone else finds the time.....
BR
Joerg
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Re: USB workaround

Postby aolofsson » Sat Sep 06, 2014 12:32 pm

Hi Joerg,
Thank you so much for digging into this!! We are in the middle of generating and verifying a new FSBL through Vivado. Once that is done we will verify your proposed workaround.
Andreas
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Re: USB workaround

Postby ESI » Sat Sep 06, 2014 1:52 pm

Hi Andreas,
is there a ps7_init.c-file within this FSBL? It usually comes with the BSP.
If you could provide it, I couls\d check, how USB init is handled...
BR
Joerg
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Re: USB workaround

Postby DAB-Embedded » Tue Sep 09, 2014 7:22 pm

Hi, on my board is the same problem with USB PHY.

My workaround: On my board U17 was not installed. U17 pad has BOARD_RESET_L pin 27, and pin 29 - P1_USB_STP. I short this pins, setup MIO42 as GPIO and reset line BOARD_RESET_L in bootloader.
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Re: USB workaround

Postby aolofsson » Tue Sep 09, 2014 8:49 pm

That is an awesome hack!!
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Re: USB workaround

Postby aolofsson » Tue Sep 09, 2014 9:06 pm

ESI wrote:Hi Andreas,
is there a ps7_init.c-file within this FSBL? It usually comes with the BSP.
If you could provide it, I couls\d check, how USB init is handled...
BR
Joerg


Joerg,
Here is the ps7_init.tcl content (jtag boot)...I will keep looking for the c file (should be the same?)
Andreas

Code: Select all
proc ps7_pll_init_data {} {
    mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
    mask_write 0XF8000110 0x003FFFF0 0x000FA220
    mask_write 0XF8000100 0x0007F000 0x00028000
    mask_write 0XF8000100 0x00000010 0x00000010
    mask_write 0XF8000100 0x00000001 0x00000001
    mask_write 0XF8000100 0x00000001 0x00000000
    mask_poll 0XF800010C 0x00000001
    mask_write 0XF8000100 0x00000010 0x00000000
    mask_write 0XF8000120 0x1F003F30 0x1F000200
    mask_write 0XF8000114 0x003FFFF0 0x000FA240
    mask_write 0XF8000104 0x0007F000 0x00030000
    mask_write 0XF8000104 0x00000010 0x00000010
    mask_write 0XF8000104 0x00000001 0x00000001
    mask_write 0XF8000104 0x00000001 0x00000000
    mask_poll 0XF800010C 0x00000002
    mask_write 0XF8000104 0x00000010 0x00000000
    mask_write 0XF8000124 0xFFF00003 0x18400003
    mask_write 0XF8000118 0x003FFFF0 0x001452C0
    mask_write 0XF8000108 0x0007F000 0x0001E000
    mask_write 0XF8000108 0x00000010 0x00000010
    mask_write 0XF8000108 0x00000001 0x00000001
    mask_write 0XF8000108 0x00000001 0x00000000
    mask_poll 0XF800010C 0x00000004
    mask_write 0XF8000108 0x00000010 0x00000000
    mask_write 0XF8000004 0x0000FFFF 0x0000767B
}
proc ps7_clock_init_data {} {
    mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
    mask_write 0XF8000128 0x03F03F01 0x00303501
    mask_write 0XF8000138 0x00000011 0x00000001
    mask_write 0XF8000140 0x03F03F71 0x00100801
    mask_write 0XF800014C 0x00003F31 0x00000721
    mask_write 0XF8000150 0x00003F33 0x00001402
    mask_write 0XF8000154 0x00003F33 0x00001402
    mask_write 0XF8000168 0x00003F31 0x00000501
    mask_write 0XF8000170 0x03F03F30 0x00100A00
    mask_write 0XF8000180 0x03F03F30 0x00100500
    mask_write 0XF8000190 0x03F03F30 0x00100500
    mask_write 0XF80001A0 0x03F03F30 0x00101900
    mask_write 0XF80001C4 0x00000001 0x00000001
    mask_write 0XF800012C 0x01FFCCCD 0x01EC084D
    mask_write 0XF8000004 0x0000FFFF 0x0000767B
}
proc ps7_ddr_init_data {} {
    mask_write 0XF8006000 0x0001FFFF 0x00000080
    mask_write 0XF8006004 0x1FFFFFFF 0x00081061
    mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
    mask_write 0XF800600C 0x03FFFFFF 0x02001001
    mask_write 0XF8006010 0x03FFFFFF 0x00014001
    mask_write 0XF8006014 0x001FFFFF 0x00041E18
    mask_write 0XF8006018 0xF7FFFFFF 0x441B50D3
    mask_write 0XF800601C 0xFFFFFFFF 0x9201C4C8
    mask_write 0XF8006020 0xFFFFFFFC 0x29289290
    mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
    mask_write 0XF8006028 0x00003FFF 0x00002007
    mask_write 0XF800602C 0xFFFFFFFF 0x00000020
    mask_write 0XF8006030 0xFFFFFFFF 0x00040550
    mask_write 0XF8006034 0x13FF3FFF 0x000104F4
    mask_write 0XF8006038 0x00001FC3 0x00000000
    mask_write 0XF800603C 0x000FFFFF 0x00000777
    mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
    mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
    mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
    mask_write 0XF8006050 0xFF0F8FFF 0x77010800
    mask_write 0XF8006058 0x0001FFFF 0x00000101
    mask_write 0XF800605C 0x0000FFFF 0x00005003
    mask_write 0XF8006060 0x000017FF 0x0000003E
    mask_write 0XF8006064 0x00021FE0 0x00020000
    mask_write 0XF8006068 0x03FFFFFF 0x00284343
    mask_write 0XF800606C 0x0000FFFF 0x00001610
    mask_write 0XF80060A0 0x00FFFFFF 0x00008000
    mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
    mask_write 0XF80060A8 0x0FFFFFFF 0x04F09896
    mask_write 0XF80060AC 0x000001FF 0x00000188
    mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
    mask_write 0XF80060B4 0x000007FF 0x00000200
    mask_write 0XF80060B8 0x01FFFFFF 0x00200068
    mask_write 0XF80060BC 0x00FFFFFF 0x00000000
    mask_write 0XF80060C4 0x00000003 0x00000000
    mask_write 0XF80060C8 0x000000FF 0x00000000
    mask_write 0XF80060DC 0x00000001 0x00000000
    mask_write 0XF80060F0 0x0000FFFF 0x00000000
    mask_write 0XF80060F4 0x0000000F 0x00000008
    mask_write 0XF8006114 0x000000FF 0x00000000
    mask_write 0XF8006118 0x7FFFFFFF 0x40000001
    mask_write 0XF800611C 0x7FFFFFFF 0x40000001
    mask_write 0XF8006120 0x7FFFFFFF 0x40000001
    mask_write 0XF8006124 0x7FFFFFFF 0x40000001
    mask_write 0XF800612C 0x000FFFFF 0x0002E020
    mask_write 0XF8006130 0x000FFFFF 0x0002C428
    mask_write 0XF8006134 0x000FFFFF 0x0002CC26
    mask_write 0XF8006138 0x000FFFFF 0x0002F41B
    mask_write 0XF8006140 0x000FFFFF 0x00000035
    mask_write 0XF8006144 0x000FFFFF 0x00000035
    mask_write 0XF8006148 0x000FFFFF 0x00000035
    mask_write 0XF800614C 0x000FFFFF 0x00000035
    mask_write 0XF8006154 0x000FFFFF 0x000000A0
    mask_write 0XF8006158 0x000FFFFF 0x000000A8
    mask_write 0XF800615C 0x000FFFFF 0x000000A6
    mask_write 0XF8006160 0x000FFFFF 0x0000009B
    mask_write 0XF8006168 0x001FFFFF 0x0000010D
    mask_write 0XF800616C 0x001FFFFF 0x00000106
    mask_write 0XF8006170 0x001FFFFF 0x00000108
    mask_write 0XF8006174 0x001FFFFF 0x00000112
    mask_write 0XF800617C 0x000FFFFF 0x000000E0
    mask_write 0XF8006180 0x000FFFFF 0x000000E8
    mask_write 0XF8006184 0x000FFFFF 0x000000E6
    mask_write 0XF8006188 0x000FFFFF 0x000000DB
    mask_write 0XF8006190 0xFFFFFFFF 0x10040080
    mask_write 0XF8006194 0x000FFFFF 0x0001FCC5
    mask_write 0XF8006204 0xFFFFFFFF 0x00000000
    mask_write 0XF8006208 0x000F03FF 0x000803FF
    mask_write 0XF800620C 0x000F03FF 0x000803FF
    mask_write 0XF8006210 0x000F03FF 0x000803FF
    mask_write 0XF8006214 0x000F03FF 0x000803FF
    mask_write 0XF8006218 0x000F03FF 0x000003FF
    mask_write 0XF800621C 0x000F03FF 0x000003FF
    mask_write 0XF8006220 0x000F03FF 0x000003FF
    mask_write 0XF8006224 0x000F03FF 0x000003FF
    mask_write 0XF80062A8 0x00000FF7 0x00000000
    mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
    mask_write 0XF80062B0 0x003FFFFF 0x000050E5
    mask_write 0XF80062B4 0x0003FFFF 0x00000E7E
    mask_poll 0XF8000B74 0x00002000
    mask_write 0XF8006000 0x0001FFFF 0x00000081
    mask_poll 0XF8006054 0x00000007
}
proc ps7_mio_init_data {} {
    mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
    mask_write 0XF8000B40 0x00000FFF 0x00000600
    mask_write 0XF8000B44 0x00000FFF 0x00000600
    mask_write 0XF8000B48 0x00000FFF 0x00000672
    mask_write 0XF8000B4C 0x00000FFF 0x00000672
    mask_write 0XF8000B50 0x00000FFF 0x00000674
    mask_write 0XF8000B54 0x00000FFF 0x00000674
    mask_write 0XF8000B58 0x00000FFF 0x00000600
    mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068
    mask_write 0XF8000B60 0xFFFFFFFF 0x0018C068
    mask_write 0XF8000B64 0xFFFFFFFF 0x0018C068
    mask_write 0XF8000B68 0xFFFFFFFF 0x0018C068
    mask_write 0XF8000B6C 0x00007FFF 0x00000E09
    mask_write 0XF8000B70 0x00000021 0x00000021
    mask_write 0XF8000B70 0x00000021 0x00000020
    mask_write 0XF8000B70 0x07FFFFFF 0x00000823
    mask_write 0XF8000700 0x000000FE 0x00000000
    mask_write 0XF8000704 0x00003FFF 0x00000702
    mask_write 0XF8000708 0x00003FFF 0x00000702
    mask_write 0XF800070C 0x00003FFF 0x00000702
    mask_write 0XF8000710 0x00003FFF 0x00000702
    mask_write 0XF8000714 0x00003FFF 0x00000702
    mask_write 0XF8000718 0x00003FFF 0x00000702
    mask_write 0XF800071C 0x000000FE 0x00000000
    mask_write 0XF8000720 0x00003FFF 0x000007E0
    mask_write 0XF8000724 0x00003FFF 0x000006E1
    mask_write 0XF8000728 0x00003FFF 0x00000680
    mask_write 0XF800072C 0x00003FFF 0x00000680
    mask_write 0XF8000730 0x00003FFF 0x00000680
    mask_write 0XF8000734 0x00003FFF 0x00000680
    mask_write 0XF8000738 0x00003FFF 0x00000680
    mask_write 0XF800073C 0x00003FFF 0x00000680
    mask_write 0XF8000740 0x00003FFF 0x00000302
    mask_write 0XF8000744 0x00003FFF 0x00000302
    mask_write 0XF8000748 0x00003FFF 0x00000302
    mask_write 0XF800074C 0x00003FFF 0x00000302
    mask_write 0XF8000750 0x00003FFF 0x00000302
    mask_write 0XF8000754 0x00003FFF 0x00000302
    mask_write 0XF8000758 0x00003FFF 0x00000303
    mask_write 0XF800075C 0x00003FFF 0x00000303
    mask_write 0XF8000760 0x00003FFF 0x00000303
    mask_write 0XF8000764 0x00003FFF 0x00000303
    mask_write 0XF8000768 0x00003FFF 0x00000303
    mask_write 0XF800076C 0x00003FFF 0x00000303
    mask_write 0XF8000770 0x00003FFF 0x00000304
    mask_write 0XF8000774 0x00003FFF 0x00000305
    mask_write 0XF8000778 0x00003FFF 0x00000304
    mask_write 0XF800077C 0x00003FFF 0x00000305
    mask_write 0XF8000780 0x00003FFF 0x00000304
    mask_write 0XF8000784 0x00003FFF 0x00000304
    mask_write 0XF8000788 0x00003FFF 0x00000304
    mask_write 0XF800078C 0x00003FFF 0x00000304
    mask_write 0XF8000790 0x00003FFF 0x00000305
    mask_write 0XF8000794 0x00003FFF 0x00000304
    mask_write 0XF8000798 0x00003FFF 0x00000304
    mask_write 0XF800079C 0x00003FFF 0x00000304
    mask_write 0XF80007A0 0x00003FFF 0x00000304
    mask_write 0XF80007A4 0x00003FFF 0x00000305
    mask_write 0XF80007A8 0x00003FFF 0x00000304
    mask_write 0XF80007AC 0x00003FFF 0x00000305
    mask_write 0XF80007B0 0x00003FFF 0x00000304
    mask_write 0XF80007B4 0x00003FFF 0x00000304
    mask_write 0XF80007B8 0x00003FFF 0x00000204
    mask_write 0XF80007BC 0x00003FFF 0x00000204
    mask_write 0XF80007C0 0x00003FFF 0x00000205
    mask_write 0XF80007C4 0x00003FFF 0x00000204
    mask_write 0XF80007C8 0x00003FFF 0x00000204
    mask_write 0XF80007CC 0x00003FFF 0x00000204
    mask_write 0XF80007D0 0x00003FFF 0x00000280
    mask_write 0XF80007D4 0x00003FFF 0x00000280
    mask_write 0XF8000004 0x0000FFFF 0x0000767B
}
proc ps7_peripherals_init_data {} {
    mask_write 0XE0001034 0x000000FF 0x00000006
    mask_write 0XE0001018 0x0000FFFF 0x0000003E
    mask_write 0XE0001000 0x000001FF 0x00000017
    mask_write 0XE0001004 0x00000FFF 0x00000020
    mask_write 0XE000D000 0x00080000 0x00080000
    mask_write 0XF8007000 0x20000000 0x00000000
}

proc mask_poll { addr mask } {
    set curval "0x[string range [mrd $addr] end-8 end]"
    set maskedval [expr {$curval & $mask}]
    while { $maskedval == 0 } {
        set curval "0x[string range [mrd $addr] end-8 end]"
        set maskedval [expr {$curval & $mask}]
    }
}

proc ps7_init {} {
    ps7_mio_init_data
    ps7_pll_init_data
    ps7_clock_init_data
    ps7_ddr_init_data
    ps7_peripherals_init_data
}

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Re: USB workaround

Postby DAB-Embedded » Wed Sep 10, 2014 9:51 am

DAB-Embedded wrote:Hi, on my board is the same problem with USB PHY.

My workaround: On my board U17 was not installed. U17 pad has BOARD_RESET_L pin 27, and pin 29 - P1_USB_STP. I short this pins, setup MIO42 as GPIO and reset line BOARD_RESET_L in bootloader.

In software i recommend to do next:
put MIO42 to GPIO mode.
set "1" in DATA reg.
enable output direction (DIR_M) and enable output driver (OEN).
set "0" in DATA reg.
wait necessary time.
set "1" in DATA reg.
set input direction (DIR_M) and disable output driver (OEN).

This algorithm avoid driving BOARD_RESET_L line whole time.
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Re: USB workaround

Postby ESI » Wed Sep 10, 2014 7:57 pm

Andreas,
in my experience c and tcl are the same. This tcl shows the same behaviour 0xf8000770++ and 0f80007a4++ are just configured in ascending order(the MIO pins for the2 USBs). And in the main routine, the MIO are configured first, and then PLLs are configured. So the behavour should be the same.
Maybe I finde the time to try this in the next days,
BR
Joerg
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Re: USB workaround

Postby Sean S » Wed Sep 17, 2014 11:46 am

Will a new image be released with instructions on a hardware mod?

Thanks
Sean
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Re: USB workaround

Postby ka6s » Wed Oct 08, 2014 6:22 pm

Has there been any progress on this - I've been stopped in my tracks with this bug.

Steve
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