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Parallella Community • View topic - Vivado default project data2mem error & timing violation

Vivado default project data2mem error & timing violation

Using Zynq Programmable Logic and Xilinx tools to create custom board configurations

Vivado default project data2mem error & timing violation

Postby kselyunin » Mon Apr 20, 2015 9:19 am

kselyunin
 
Posts: 2
Joined: Mon Apr 20, 2015 8:41 am

Re: Vivado default project data2mem error & timing violation

Postby mafleming » Sat May 02, 2015 7:25 pm

I too saw the same set of warnings when building the project (Vivado 2014.4 on Windows 7 64-bit). Taking the advice to ignore warnings on the blog post, I copied the newly built bitstream file to the SD boot sector and fired up the Parallella. The board booted and Epiphany examples run without a hitch.

I'm new to Vivado and my ISE experience dates back to 12.4, so I can't provide details on your other questions without consulting the docs and knowledge base, but at least the answer to #2 is Yes!

Cheers,
~ Mark
mafleming
 
Posts: 6
Joined: Tue Feb 17, 2015 11:03 pm

Re: Vivado default project data2mem error & timing violation

Postby kselyunin » Wed May 27, 2015 12:32 pm

Ok, thank you Mike!
kselyunin
 
Posts: 2
Joined: Mon Apr 20, 2015 8:41 am


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