Routing additional Zynq hard block I/O to PEC_FPGA

[parapara]

[frank_buss]

I would like to have all IO pins as GPIO. But you can add the other functions as alternate functions. I don't know how full the FPGA is, but a simple mux shouldn't need much logic.

From Linux the infrastructure for pin muxing is already in the kernel:

https://www.kernel.org/doc/Documentation/pinctrl.txt

The driver and FPGA backend for it should be simple, just a few registers to set the function of each pin, with GPIO as default. If there is not enough logic available to mux it to any pin, it should be at least possible to disable it and use the GPIO function for a pin. But if the FPGA has still some room, you could fill it up with as many SPI, CAN etc. modules as you want.

[yanidubin]

Frank - I had the very same thought a few days back, and since you have also suggested it, I thought I would see if I could revive the discussion .

I think the lack of pinmuxing is a very unfortunate limitation of the Zynq, and one which could be quite effectively resolved.