A few requests for the FPGA design

Using Zynq Programmable Logic and Xilinx tools to create custom board configurations

A few requests for the FPGA design

Postby tnt » Tue Jun 10, 2014 12:05 pm

Hi,

Here's a list of what I'd like to see happen :

* Better encapsulation

By this I mean both refrain to use too generic names. I mean 'axi_master' is a pretty generic name for something that's completely specific to the eLink. I think something like emesh_axi_master or elink_axi_master would be more appropriate.

I also mean that the whole AXI <-> eMesh should be a module in itself, something pretty self contained that can be copied to another project. Currently you have to copy several subdirs and correctly interconnect them. Or maybe that's what parallella.v is supposed to be ? But then I would still comment that the name isn't great (because it's just the elink part and not the whole parallella design) and I'd make sure the directory reflects that (i.e. don't have the parallella_z7_top.v top level in the same dir).

Something like :

hdl/
top/
parallella_z7_top.v
elink/
elink_top.v
axi/...
phy/...
utils/...

So that you can easily just copy elink/ to your own project, wire the two AXI to the PS7 and the other wires to the pads and you get a working elink in your project.

This could even be a submodule with it's own vivado tcl script to set-it up so that updates are easier.

* Improved compatibility with the Rev 0 board.

Using generic (or whatever the verilog equivalent is), it should be fairly straight forward to have this AXI <-> eMesh wrapper to support both Rev0 and Rev 1.x boards. They might not be the best from a power PoV but they work just fine and it's a bit of a waste not to allow those who have some to use it.

* Work with the Vivado flow

My last attempt at this yielded some 'logic loop' during synthesis ... no idea what was going on since my verilog isn't all that good (I'm a VHDL guy :)


Cheers,

Sylvain
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Re: A few requests for the FPGA design

Postby aolofsson » Tue Jun 10, 2014 7:03 pm

sylvain,
Great inputs! A hierarchy reorg and moving to vivado are on the very soon todo list. We are still trying to check off one thing at a time...
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Re: A few requests for the FPGA design

Postby bithead » Wed Jun 11, 2014 5:04 pm

I'd like to request a "nice-to-have" thing for us FPGA hobbyists that are also somewhat (less than 3 years of hobbyist exp) new to the whole hardware design thing --

An example project that shows how to add our own designs alongside the Parallella eLink stuff. The warnings about pin constraints are kind of dire and scare people like me; if there was a sample project that added something to the design that I could use as a base for my own design, or maybe even just a blank template I could use as a starting point, I'm sure a lot of us who bought the Parallella for more than just the Epiphany chip would be very happy.
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Re: A few requests for the FPGA design

Postby xilman » Thu Jun 12, 2014 9:15 am

bithead wrote:I'd like to request a "nice-to-have" thing for us FPGA hobbyists that are also somewhat (less than 3 years of hobbyist exp) new to the whole hardware design thing --

An example project that shows how to add our own designs alongside the Parallella eLink stuff. The warnings about pin constraints are kind of dire and scare people like me; if there was a sample project that added something to the design that I could use as a base for my own design, or maybe even just a blank template I could use as a starting point, I'm sure a lot of us who bought the Parallella for more than just the Epiphany chip would be very happy.
+1 to this. I've << 3years experience and a little handholding will go a long way.

Paul
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Re: A few requests for the FPGA design

Postby Transcendental » Fri Jun 13, 2014 2:32 pm

bithead wrote:I'd like to request a "nice-to-have" ... an example project that shows how to add our own designs alongside the Parallella eLink stuff ... if there was a sample project that added something to the design that I could use as a base for my own design ... I'm sure a lot of us who bought the Parallella for more than just the Epiphany chip would be very happy.


+1
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Re: A few requests for the FPGA design

Postby FHuettig » Fri Jun 13, 2014 5:41 pm

tnt wrote:Here's a list of what I'd like to see happen


Hi Sylvain,

All excellent points. About the encapsulation, the parallella.v block is really the encapsulation of all the epiphany-related stuff, the only things the top level needs to do is instantiate the PS and connect the AXI signals to parallella.v, pretty much as you describe. Other things like the GPIOs are optional and easily changed by the user, and that's in its own module & directory. Deriving new projects does require you to include several directories, but why not just copy the entire /hdl dir.? I thought about putting them as subs under a single hdl/parallella folder, but I'd prefer to leave it as-is to support possible reuse, maybe, I'll think about it again. It's a personal style thing but I like the way it's laid-out now and as I generate new projects they simply sit in the 'projects' folder and any new rtl goes in the hdl directory alongside the existing blocks. Nothing gets moved and the new project refers to everything it needs in-place.

I do agree that the top-level file should be out of the parallella directory.

I also agree some of the naming is not the best, but as long as -you- use detailed names for your own blocks and signals they won't collide with the existing ones. Can you tell I'm trying to avoid doing work? :oops: I can see changing some module names to make them more descriptive, I want to keep the signal names on the PS interface signals because they are defaults from the EDK and few things annoy me more than having more than one name for the same signal within a module.

Regarding the Rev. 0 board, I don't think there are enough of them in the wild to make it worth the effort, sorry. There certainly aren't any being sent out.

Finally, on Vivado, as Andreas said we are working on that but when I tried even to update everything to ISE 14.7 it opened a can of worms because the FSBL and u-boot wouldn't play with our linux image correctly, so everything needs to be updated at once. But we are working on that actively. Making the elink interface a pcore of its own would be slick, especially if we can add another port or two to allow user data in/out, e.g. a FIFO block that could take video or radio data and scatter it to the e-processors and/or pick up results. That's what I dream about.

Cheers!

BTW I started out as a Verilog guy, but after doing a lot of VHDL over the past 10 years now I wish everything was in VHDL. I spent a couple of days this winter tracking down bugs in someone else's Verilog that would have been immediately flagged as errors by VHDL. I still understand the attraction of Verilog, but also have learned the advantages of VHDL.
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Re: A few requests for the FPGA design

Postby FHuettig » Fri Jun 13, 2014 6:15 pm

bithead wrote:I'd like to request a "nice-to-have" thing for us FPGA hobbyists that are also somewhat (less than 3 years of hobbyist exp) new to the whole hardware design thing --

An example project that shows how to add our own designs alongside the Parallella eLink stuff. The warnings about pin constraints are kind of dire and scare people like me; if there was a sample project that added something to the design that I could use as a base for my own design, or maybe even just a blank template I could use as a starting point, I'm sure a lot of us who bought the Parallella for more than just the Epiphany chip would be very happy.


Hi guys, I'm happy to hear that you are interested in working with the Zynq and epiphany together. I have hoped that the project we have would serve as a good example by itself. Not as a basic tutorial on how to use the Xilinx tools and certainly not as a basic Verilog tutorial, both of those exist in abundance, but if you want to add your own logic to the Parallella design just look at the top level file (parallella_z7_top.v) and see how all the epiphany-related stuff in parallella.v and the Arm processor system (a/k/a PS) connected through the system_stub black box module are connected together and to the outside world.

The best place to start is probably the parallella_gpio_emio module, if you are doing your own logic to interface to the outside world you'll be using the GPIO pins. That module is very simple, you should be able to add your own logic in a clone of that block if you don't need to interface directly to the arms or the epiphany. You can use the GPIO signals from the PS and access them from linux without having to write any drivers or change the devicetree, simple! Adding an interface directly to the PS bus requires talking to the AXI and adding the interface in the EDK, then changing the system_stub block to add the interface signals. It's not for the faint of heart nor can I do the subject justice in a forum posting or an example, but there is a lot of literature available from Xilinx to get you going on more sophisticated use of the Zynq, it's a powerful but complex beast!

As for the dire warnings about the pin constraints, if you start with an existing project (pick your device and whether you want HDMI or not) and copy that to a new project (I recommend un-checking the "copy files to project" box so the existing sources stay where they are) you'll be safe because the new project will have the tried-and-true constraints. Just don't change the constraints unless/until you know that you need to. Same with the direction and iostandards of all the non-GPIO pins like the HDMI signals, don't change those (you can't use them for different puposes anyway!)and you'll be OK. You should also know that the IO standards for the GPIOs are currently set in the Verilog module rather than the constraints files (so they can be changed for different projects). If you don't do it the same way they'll default to LVCMOS_25 (2.5V logic) and actually that will be OK, if you try to use a different standard like LVCMOS_33 you'll also have to change the HDMI pins or the Xilinx tools will throw an error, either way your Parallella board will be safe. The biggest danger comes from defining a pin as an output and then connecting it to the output of another device, stick to the low-current settings on the IO pins and even with a conflict you probably won't do any damage. Be sure to double-check your pin assignments, it may be unlikely you'll damage the Zynq but it's not covered by the warranty!

If this still isn't helpful then let me know what you are trying to do and maybe I can provide more directed help.

Best,
Fred
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Re: A few requests for the FPGA design

Postby tnt » Sun Jun 15, 2014 11:31 pm

FHuettig wrote:All excellent points. About the encapsulation, the parallella.v block is really the encapsulation of all the epiphany-related stuff, the only things the top level needs to do is instantiate the PS and connect the AXI signals to parallella.v, pretty much as you describe. Other things like the GPIOs are optional and easily changed by the user, and that's in its own module & directory. Deriving new projects does require you to include several directories, but why not just copy the entire /hdl dir.? I thought about putting them as subs under a single hdl/parallella folder, but I'd prefer to leave it as-is to support possible reuse, maybe, I'll think about it again. It's a personal style thing but I like the way it's laid-out now and as I generate new projects they simply sit in the 'projects' folder and any new rtl goes in the hdl directory alongside the existing blocks. Nothing gets moved and the new project refers to everything it needs in-place.


Essentially what I'd like for when it's on vivado is to have an 'IP' block that can be dragged in their 'IP integrator' and just have the pads to the epiphany and the two AXI interface.

This would also make it much simpler to add an AXI interconnect block between the PS and the e-link interface to allow other blocks to write to the epiphany directly and all the arbitration and queuing would be done by pre-made IPs from Xilinx.

FHuettig wrote:Regarding the Rev. 0 board, I don't think there are enough of them in the wild to make it worth the effort, sorry. There certainly aren't any being sent out.


Well "the effort" is pretty trivial. The only change is the UCF (which already exists, I already have version of both for vivado btw) and then one signal which is differential or not so this essentially only need an option to include or not a differential buffer for that signal.

FHuettig wrote:Finally, on Vivado, as Andreas said we are working on that but when I tried even to update everything to ISE 14.7 it opened a can of worms because the FSBL and u-boot wouldn't play with our linux image correctly, so everything needs to be updated at once.


Really ? What did they change ?

I only tried building the bitstream so far with vivado (back in 2013.4 IIRC) and the synthesis kept throwing "Logic loop detected" warning in the FIFO but I couldn't trace where or why it was saying that ...
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tinkering with fpga

Postby over9000 » Mon Jun 16, 2014 12:07 am

I'm sorry if this is a very newbie question, but if I wanted to change part of the FPGA logic, would it be possible to simply write some new code to target unused parts of the chip (pins + logic), or does the entire bitstream (plus my modifications) need to be recompiled at the same time? If it's the latter, is a reboot needed to reprogram the FPGA?
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Re: tinkering with fpga

Postby FHuettig » Mon Jun 16, 2014 4:36 am

over9000 wrote:I'm sorry if this is a very newbie question, but if I wanted to change part of the FPGA logic, would it be possible to simply write some new code to target unused parts of the chip (pins + logic), or does the entire bitstream (plus my modifications) need to be recompiled at the same time?

The entire chip needs to be built each time. This includes the not just the PL fabric but also the interface to the Arm processors and peripherals so you have to run the edk even if you're not changing anything to do with the PS.

There is a concept of "partial reconfiguration" but I have not studied it. I think you may still have to build everything in the design, and it just creates a bitstream that leaves unchanged parts of the chip alone while re-writing others. I think this also requires a license beyond the WebPack.

You mention "unused parts of the chip (pins + logic)" but be aware that there are no unused pins currently. The GPIO pins may be re-purposed for your own use, but they are connected in the standard projects.

over9000 wrote:If it's the latter, is a reboot needed to reprogram the FPGA?


No, the FPGA can be reconfigured from the Linux command line. This assumes the logic fabric is not actively doing something like generating the HDMI video stream, so if you are using an HDMI-based system you do have to reboot (putting your new binary bitstream into the BOOT partition of the SD card as "parallella.boot.bin". But with a headless system you can write the bitstream (either .bit or .bit.bin) directly to /dev/xdevcfg. There seems to be a caveat about how many times you can do this without rebooting (see this posting).
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