ARM FPGA communication

[yanidubin]

Yes, those warnings do look familiar - I am sure I encountered the same issue. The problem is this was a few weeks ago now, and I really can't recall what the fix was. I'd be totally guessing. But since I'm going to go through this tomorrow as I finish writing the tutorial, I expect I'll solve it all over again - sorry about the wait!

Okay, I had a quick look at a diff of a good working project versus what I got on a fresh project.

It seems on both my AXI4Lite and AXI4 projects, I am using the other bus interface, which is not enabled by default. That is, M_AXI_GP0 rather than M_AXI_GP1.

The difference in the system.mhs which I think is relevant is:
< BUS_INTERFACE M_AXI_GP1 = axi_interconnect_1
---
> PARAMETER C_USE_M_AXI_GP0 = 1
> BUS_INTERFACE M_AXI_GP0 = axi_interconnect_1

I spent some time comparing the XPS sources between Parallella and Zedboard working that one out. I can't remember why I concluded this was needed.

I don't like giving directions without testing them myself, but it is late and I think there is a good chance this may sort you out. Good luck, and I will definitely get to the bottom of it tomorrow if this does not resolve it for you

You can implement these changes by just editing your file (easiest) - or you can double click 32b GP AXI Master Ports at the lower left of the system diagram (The one on the Zynq tab in XPS) and enable GP0, then go to the Bus Interfaces tab and assign axi_interconnect_1 to M_AXI_GP0.

[AndyC]

Hi Yanidubin,

Thanks very much, I will have a look and see.

All the best

Andy

[theover]

Of course it would be nice to Free and Open Source cover a decent recap of 80s Network theory in the context of chip design databases and automation tools (like a part of my EE education at the time), but honestly, I don't care for a demonstration of people trying to bring a AppleII design up to date with the provided Zynq tools, so I'd be more interested in the exact dealings with the questions at hand:: how are the addresses turned into fixed or alterable FPGA connectivity, what are the connected latencies and bandwidths, how does the software need to connect ((are there interupt handlers and if so what are the demands on them and where do they reside/can they be updated), and what part *must* but done with the Xilinx tools, besides the basic connections of the existing projects, and the buffers and data-size adaptations?

So I would be most helped with an example like: here's the Epiphany interface so-and-so, these address ranges are free, the handler can be added and compiled here or so-ana-so, and the glue holds if these and these conflics are prevented. The rest is dancing about trivialities I don't care for,but maybe others do.

T.

[yanidubin]

Hi Theo - I think I hear what you are saying in terms of separating the (interesting) technique from the (mundane) application of the technique. I intend a minimal demo covering how to connect up a peripheral (which people can then go and use to develop their own cool projects), and a minimal of modification so that someone running through it can do the equivalent of toggling an LED (store operands, set instruction, read result). If I was to write a tutorial covering how to implement a more complete ALU (an intentional reinventing of the wheel for fun / instructional value), then this would be quite separate.

As to your other points, I think I may have to disappoint you, since you probably need an expert (which I am not). At present, I can't satisfy your curiosity about performance, but in time this may change.

Also, at this stage I only intend to cover the most basic way of interfacing from the Linux side (/dev/mem, rather than writing a dedicated driver to interact with the registers, and adding interrupts - I believe this is quite possible). I'm putting off writing drivers until I get AXI-stream working (a high performance DMA based mechanism), which is what I have been aiming for all along, however success with this has eluded me thus far (and it is currently on the backburner while I write this stuff up, and then get back to work on my robotics project - but sooner or later someone, maybe myself, will get this working).

There are two reasons I haven't tested the bandwidth of what I've implemented - firstly, it isn't a high performance interface, and I always intended to produce the FPGA equivalent of the matmul example - but I wanted to show the FPGA to advantage there. Secondly, I doubt using /dev/mem rather than a dedicated driver is the most efficient way to access this - but haven't looked into the options here.

As I'll state in my tutorial, these are just my learnings from tutorials for the Zedboard/Zync over the last few weeks in general presented in a digestible format for the Parallella with various hurdles smoothed over. I'm not presenting these because I am an expert (I did minimal VHDL during my EE degree, and this was 7yrs ago already - I'm tinkering with the FPGA to flake off the rust, improve those skills, then put them to use). Since enough people have registered interest in getting a leg up on this stuff, my aim then is to lower the barrier to entry (by giving a Parallella tailored intro), and once people start interacting with the FPGA, then they can (and should) go elsewhere and learn from more general tutorials. Hopefully we'll see more people discussing the FPGA stuff in the forums (not that I want to take attention away from the Epiphany - each has its place).

[cmcconnell]

I'm interested in the FPGA side of things too. In fact I originally discovered the Parallella in this list - http://www.joelw.id.au/FPGA/CheapFPGADevelopmentBoards - while researching FPGA dev boards. The Epiphany was a sort of added bonus!

But up to now I've actually been focusing entirely on the Epiphany. I was planning to wait for the update to Vivado before turning my attention to the Zynq. But if that is still some way off, then an idiot's guide to getting started with ISE and the Parallella would certainly be welcome.

[yanidubin]

Continuing discussion with AndyC on his other , since that is dedicated to the particular issue he is facing (a difference in the HDMI and headless projects).

[yanidubin]

For everyone who was hanging out for my tutorial - it is now up, and you can find it via .