Using M_AXI_GP0 of PS [Solved]
Posted: Fri Oct 09, 2015 12:47 pm
Hi,
I am using the Parallella FPGA design provided by Adapteva, but I have to add things to it. Do do that, I need one of the AXI master ports of the PS. There are only two (M_AXI_GP0 and M_AXI_GP1) and they are both connected to the eLink interface. I tried changing the design so that one of those two goes to an AXI Interconnect that has one input and two outputs. From there they each go to one of the two ports of the eLink interface. Can this work? I have the feeling that I have to change something in the Address Editor, but I don't know what. If it does, why isn't this the default? It's quite likely that someone needs that port. I didn't have time to test anything on the Parallella itself, but it would already be a huge help if I knew that this COULD work. Otherwise I'm debugging something for hours that couldn't have worked in the first place.
Thanks,
Alain
PS: I'm using Vivado 2015.2
I am using the Parallella FPGA design provided by Adapteva, but I have to add things to it. Do do that, I need one of the AXI master ports of the PS. There are only two (M_AXI_GP0 and M_AXI_GP1) and they are both connected to the eLink interface. I tried changing the design so that one of those two goes to an AXI Interconnect that has one input and two outputs. From there they each go to one of the two ports of the eLink interface. Can this work? I have the feeling that I have to change something in the Address Editor, but I don't know what. If it does, why isn't this the default? It's quite likely that someone needs that port. I didn't have time to test anything on the Parallella itself, but it would already be a huge help if I knew that this COULD work. Otherwise I'm debugging something for hours that couldn't have worked in the first place.
Thanks,
Alain
PS: I'm using Vivado 2015.2