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Synthesis Error:loop statement with empty body is not permit

PostPosted: Sat Jun 02, 2018 1:33 am
by Min
I'm trying to update parallella-fpga project to use the latest Vivado. After updating Xilinx ip, I final able to Open Block Design. But when I try to Synthesis the project. I got this error:

[Synth 8-2300] loop statement with empty body is not permitted in this mode of verilog ["parallella/parallella-fpga/7020_hdmi/7020_hdmi.srcs/sources_1/bd/elink2_top/ipshared/c2c9/src/oh_mux.v":24]

I'm not expert of verilog/Synthesis. Does anyone know how to solve this problem?


Re: Synthesis Error:loop statement with empty body is not pe

PostPosted: Wed Jun 06, 2018 5:25 am
by dipin
HI ,

please check the oh_mux.v file in the src folder. when i tried to use the vivado2018.1 for parallella project which is built in 2015.4 version.. it was not all working, there is so many errors like "system_i is missing". this is due to version control problems. i think you know about it. i fixed it by getting astable version and switch back to 2015.4 vivado. so can you check like "in side for loop, is there supposed to be any code". and did you opened your main vivado program or packaged ip.
in my packaged ip, oh_mux.v is also throwing some syntax error. but i am not using oh_mux.v.