Vivado(_hls) 2019.2 , Anyone ?

Using Zynq Programmable Logic and Xilinx tools to create custom board configurations

Vivado(_hls) 2019.2 , Anyone ?

Postby theover » Sat Dec 07, 2019 12:25 pm

Hi all,

Very quiet here, it almost feels like an antiquarian.

I plan to put my 7010 board to good use though with the new Vivado, which includes partial reprogramming. I've used Vivado before here, like https://parallella.org/forums/viewtopic.php?f=51&t=3376&sid=d246bd05f124e0558743ceb4b4d3ed0f, but it seems the high level language "Silicon Compilation" are taking off, and I like to make use of them on this cheap board before having to use for instance AWS credit for an F1 node.

Anyone try example projects on recent Vivado ?
THey seem to have just about every board as a design template, except for the Parallella, why so spartan, doesn't it sell anymore?

Theo V
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Re: Vivado(_hls) 2019.2 , Anyone ?

Postby ajtravis » Sat Dec 07, 2019 3:30 pm

theover wrote:Hi all,

Very quiet here, it almost feels like an antiquarian.

I plan to put my 7010 board to good use though with the new Vivado, which includes partial reprogramming. I've used Vivado before here, like https://parallella.org/forums/viewtopic.php?f=51&t=3376, but it seems the high level language "Silicon Compilation" are taking off, and I like to make use of them on this cheap board before having to use for instance AWS credit for an F1 node.

Anyone try example projects on recent Vivado ?
THey seem to have just about every board as a design template, except for the Parallella, why so spartan, doesn't it sell anymore?

Theo V


Hi, Theo.

As I mentioned in my USB message: I'm learning about Vivado and I'd appreciate any advice you have about using it with Parallella...

Thanks,

Tony.
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Re: Vivado(_hls) 2019.2 , Anyone ?

Postby theover » Sat Dec 07, 2019 8:00 pm

Hi Tony, it's a matter of me having the interest to run "silicon compilation" which is possible through Vivado/Vidado_hls (and the new Vitis).

First, it's important to get the parallella design through the motion of putting something in the FPGA that works, and can connect with a C program which runs on the Parallella A.R.M. processors. I've used examples years ago, which worked with Vivado, and now (today in fact) I've upgraded a simple project for an adder block being connected through an AXIlite bus from years ago to the latest Vivado 2019.2, and in essence: I've just connected a (very) big heatsink to the Zynq chip, loaded the new Vivado generated .bit file in it, tried the test program: and it appears to work!

Theo
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Re: Vivado(_hls) 2019.2 , Anyone ?

Postby theover » Wed Dec 25, 2019 3:29 pm

It's very quiet, but for those interested: I also got to include a C-function from Vivado_hls in my project to run on the Parallella hardware, such that in this case I included a C function with a lite AXI interface, which can get vivado compiled, and runs on my Parallella board when loaded in. Less script driven then e.g. in aws cloud FPGA setup, and a much humbler board, but the compile time is bearable on a fast PC, and there appear to be no major problems, except getting vivado hls to understand what parallel and pipe-lining constructs to implement. If someone is interested in including the high level language part with the board design, I can give a little explanation.

TV
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Re: Vivado(_hls) 2019.2 , Anyone ?

Postby ajtravis » Wed Dec 25, 2019 3:56 pm

theover wrote:It's very quiet, but for those interested: I also got to include a C-function from Vivado_hls in my project to run on the Parallella hardware, such that in this case I included a C function with a lite AXI interface, which can get vivado compiled, and runs on my Parallella board when loaded in. Less script driven then e.g. in aws cloud FPGA setup, and a much humbler board, but the compile time is bearable on a fast PC, and there appear to be no major problems, except getting vivado hls to understand what parallel and pipe-lining constructs to implement. If someone is interested in including the high level language part with the board design, I can give a little explanation.

TV


Hi, Theo.

Good to see at least one other still interested in Parallella ;-)

So far, I've bought a JTAG-USB adapter but crashed and burned trying to install Vivado on my laptop :-(

Merry Christmas!

Peace and goodwill to all mankind,

Tony.
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Re: Vivado(_hls) 2019.2 , Anyone ?

Postby theover » Wed Jan 08, 2020 2:50 pm

Talking about goodwill to mankind, I did a video example of a Silicon compile/test with the Parallella and the vivado design files:

https://youtu.be/kfWNfjcIO2Q "Vivado HLS demonstration C function to FPGA"

Cheers,

Theo V.
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Re: Vivado(_hls) 2019.2 , Anyone ?

Postby ajtravis » Wed Jan 08, 2020 4:55 pm

theover wrote:Talking about goodwill to mankind, I did a video example of a Silicon compile/test with the Parallella and the vivado design files:

https://youtu.be/kfWNfjcIO2Q "Vivado HLS demonstration C function to FPGA"


Hi, Theo.

Just watched your video - Thanks for posting it and giving me a realistic idea about what's involved in silicon programming for the FPGA!

Not quite sure if I'm impressed or intimidated ;-)

Happy New Year!

Tony.
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Re: Vivado(_hls) 2019.2 , Anyone ?

Postby theover » Wed Jan 08, 2020 5:16 pm

I hope not you're feeling intimidated, though I must say it took me explicit directions like years ago to put the correct Vivado project together, and it's a bit of a hassle to understand all the protocol and IP flow steps needed, actually a bit hard to find.

On the other hand, it does really work and is *logical*, albeit maybe not straightforward.

Thanks for watching, I though I'd make it a bit more digestible by making some music in the background.

Theo
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