Figuring out where addresses comes from?

[mkaczanowski]

Hey,
I don't have much knowledge about the FPGA, so I tried to understand parallella design a bit more by looking at Vivado project and kernel module sources.

There are a few addresses there:
1. parallella_slave_axi - 0x80000000
2. memory range owned by kernel:
```
/* First range is FPGA config regs.
* Second range is mappable emesh region
*/
reg = <0x81000000 0x100000>, <0x80000000 0x10000000>;
```
3. mmu setting
adapteva,mmu = <0x8e000000 0x3e000000 0x02000000>;
emesh_start, phys_start, size
```

So I am trying to figure where each address came from:
1. axi_slave address (0x80000000) is CPU memory mapped, so no questions here
2. FPGA Config regs, offset: 0x81000000 - I don't quite get why offset is set to 0x81000000 and where is it defined?
In the C library the 0x81000000 is used as eLink base and that makes a lot of sense, however where it's defined in verilog that eLink should be placed at this address? I only found the relative addressing: https://github.com/aolofsson/oh/blob/ma ... _regmap.vh
3. mappable eMesh region = offset: 0x80000000, size: 0x10000000. I think I understand that as: 4 elinks (west, north, ...) * 64 cores * (1<<20) mappable memory per core
4. MMU / shared memory - there is 32mb of shared DRAM. Where emesh_start: 0x8e000000 and phys: 0x3e000000 comes from?

If you could help me figure out where this addressing comes from (mostly the base addresses, that would be helpful)

Thanks,
Mateusz

[mkaczanowski]

Okay, I got the answers on my own. If anyone is as curious as I am here is the post:
http://mkaczanowski.com/parallella-part-3-kernel/