Programming the Adapteva Epiphany 64-core NoC Coprocessor

Announcements of academic papers and technical reports based on Parallella or the Epiphany architecture.

Programming the Adapteva Epiphany 64-core NoC Coprocessor

Postby aolofsson » Wed Nov 26, 2014 2:06 am

Title: Programming the Adapteva Epiphany 64-core NoC Coprocessor


Authors: Anish Varghese, Bob Edwards, Gaurav Mitra, Alistair P. Rendell

Publication: 14 pages, submitted to IJHPCA Journal special edition

Affiliation: Australia National University

Source code: Not yet

Notes: Stencil, matrix multiplication, assembly optimization
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Re: Programming the Adapteva Epiphany 64-core NoC Coprocesso

Postby evalero » Tue Dec 01, 2015 3:30 pm

abstract = {With energy efficiency and power consumption being the primary impediment in the path to exascale systems, low-power high performance embedded systems are of increasing interest. The Parallella System-on-module (SoM) created by Adapteva combines the Epiphany-IV 64-core coprocessor with a host ARM processor housed in a Zynq System-on-chip. The Epiphany integrates low-power RISC cores on a 2D mesh network and promises up to 70 GFLOPS/Watt of processing efficiency. However, with just 32 KB of memory per eCore for storing both data and code, and only low level inter-core communication support, programming the Epiphany system presents several challenges. In this paper we evaluate the performance of the Epiphany system for a variety of basic compute and communication operations. Guided by this data we explore various strategies for implementing stencil based application codes on the Epiphany system. With future systems expected to house 4096 eCores, the merits of the Epiphany architecture as a path to exascale is compared to other competing power efficient systems.},
address = {Phoenix, USA},
archivePrefix = {arXiv},
arxivId = {1410.8772},
author = {Varghese, A and Edwards, B and Mitra, G and Rendell, A P},
booktitle = {Parallel Distributed Processing Symposium Workshops (IPDPSW), 2014 IEEE International},
doi = {10.1109/IPDPSW.2014.112},
eprint = {1410.8772},
isbn = {978-1-4799-4116-2},
issn = {23321237},
keywords = {coprocessors,network-on-chip,reduced instruction s},
pages = {984--992},
title = {{Programming the Adapteva Epiphany 64-Core Network-on-Chip Coprocessor}},
url = {},
year = {2014}
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