64core version

[piotr5]

I know. the problem I see is that compiler doesn't like it when 2 objects have the same address. for example with compressed sensing, you have a matrix of limited size in one direction and quite infinite size in the other. you use this matrix for transforming a small vector into a sparse large vector or a large vector into a small vector, through multiplication. now assume the large vector doesn't fully fit into memory. how are you supposed to program anything alike to matrix-multiplication when matrix and vector live on disc? if the output is a sparse vector, how do you know which entries are non-zero? how do you address the correct row if the index is beyond 32bit address-space on the 32-bit processor? virtual memory is a bad solution here. as I said, on single-processor this problem is solved by working inside of some disc-buffer. with epiphany the disc-buffer is spread throughout all cores! highly parallellizable task, but how do you make the code readable?

[dobkeratops]

[piotr5]

yes, that's alsoo my main concern: if you write centralized sourcecode for the algorithm and hide the details elsewhere, I somehow doubt gdb is fit for that task. you'd need to define several layers of abstraction into your program, and in the same way as you now can choose between single-stepping assembler and code, you should get the possibility to skip stepping into some functions based on the file they're contained in. i.e. single-step only c++ files and not headers. and the problem of tracking data which has no physical location in ram (but instead on disc) too requires some improvements in gdb.

anyway, concretely I tried to implement a program searching for prime-numbers. eventually memory is full, so disc-space is used for storing them. the goal is to fill a 4TB disc with prime-numbers and divisors of non-primes. (i.e. crack weak encryption in constant time.) writing and reading disc is a parallell process. you initiate it and eventually hardware has done the job while CPU continues working. so I wrote a class emulating the behaviour of a vector. but then I started thinking: eventually those 4TB are full, maybe I'll add new drives but in effect drives located in the net are a better solution. so if I want a really huge array of divisors, with the computer working several years on its creation, how do you index that? what is a realistic index-width? if after years you notice you want to continue doing this for centuries, how do you change index-width? maybe work without any index at all? but then, how does a container look, indexed by a truely arbitarily large number? the number could become so large that the index for the array storing that index for my primes becomes bigger than 64 bit? in other words, in c++ the major problem is that if the developers of some lib didn't even think of making some constants changeable, you need to copy their code and implement that adjustment yourself. (beware of closed-source code then.)

so in the end I do wish for a better programming language than c++. but instead of limiting its freedom, it should enhance it! just take the headers provided by a lib, tell the compiler what changes you want, and the binary-format lib will then work with all these changes! and I mean that not just for classes, sometimes functions perform 2 tasks that could easily be split into 2 functions. if there is a way of seeing functions as classes, then this kind of splitting should be accessible through the dot-notation...

in other words, imho all sequential stuff should be banned from functions and put into some other variable-type. anybody seen something like that?

[dobkeratops]

[rpiswag]

Adapteva how much do you need? If a theoretical 128 core or 256 core Parallella board is $2k or under I would buy it right now.

[piotr5]

why do you ask? put 16 parallella servers in a network and you get 256 cores for that price. if you want something without lag, the price naturally would be higher than 2k$. 2.4k$ is minimum if you connect parallellas through connectors or soldering. a single chip with 256 would need to cost more as otherwise it would interfere with sale of 16 core chips. and beside all that, adapteva would need to earn a total of 1 million$ or something in addition to to the actual procuction and selling of such 256 core systems, so they can pay for research costs and for buying machines to create the chips. how many people right now would be willing to buy a 256 core board? how many pieces? let's say they can sell 100 pieces, then each buyer would need to pay 10k$ in addition to the production cost. and there still is no os-support, no finished libs, no finished compiler support, nothing to actually use that chip. why would anybody want to spend that much money for 256 cores if you can buy 16x16core boards for <2k$? and there's competition: I said many times, amd's kaveri and godvari can have up to 32 risc cores with 512 bit each, for 150$ per chip. not to mention the 4x4Ghz intel-compatible processor you get in addition. put it on 35$ mainboards, and if you solve the cooling and power-requirements problem you get a cluster of 8 such computers for about 1600$ and the same set of problems (no OS no compiler, no finished lib-support) as with parallella, although at higher watt-cost and heat-generation. current parallella is slightly more expensive at first but might ammortize over time. also I'm not sure amd can really offer full 32x512bit @ 900Mhz. all in all, there's no economical reasons for a 256core processor yet. the competition is too strong to be faced without an investor giving adapteva money up front, don't know how many APU of this new generation amd has sold, but I suspect it's more than adapteva did, even though adapteva has the better product. the reason is, there's software for the intel-compatible side of amd's apu, with epiphany you can't do anything else than to program it yourself. in this situation, why would an investor want to support adapteva? therefore if you really wish to get 256core chips, you'd better pay those 2k$ to some programming for the urgently needed software-support of current 16core parallella! as was offered: for each function in pal exceeding current implementation you get a parallella, so pay someone to do 16 contributions for you, in under 2k$...

[dobkeratops]

[jlambrecht]

Given the formentioned, are there any design where a parallella board is provided as a SOM so one could simply connect many SOM to a single carrier board ?

[piotr5]

you'll find my reply and proposal for 4k core som in the other forum where you also posted that idea...