if you really are in favour of a simd epiphany then you haven't understood what I meant when I said it's cheating. the point of adapteva is that simd can never be used to full extent, mimd can. it's true that the size saved could be turned into memory, but I doubt there will ever be more than 64Kb per core. on x86 it is rare to find any in-core-cache bigger than 64k, 64k is happy with some 16-bit addressing, and instructions coping with 17 bit but not 32bit are rare -- so I guess in terms of hardware it is awkward to implement. what could happen though is adapteva adds some of amd's hbm-chips on top of epiphany to provide some sort of 2nd level cache. if then the connection between arm and epiphany could be increased to appropriate speed then this actually could become the main memory instead -- the only problem is to do this in open-source hardware...
so, I said I'd like them to go simd just because it would attract all those idiots who believe simd to be the future, of which there are many. as was said in the tokyo-talk, for server-people to notice you the processor either needs x86 compatibility or it must be simd with compatibility to the graphics-cards. with risc-processor the latter truely is a possibility. sadly the most attractive solution isn't always the solution that will survive in future, peers can err, the hievemind isn't infallible. take for example vhs and whatever other tape-format: it's cd which survived, at least its aspect of having some digital data-format! it simply is the most pragmatic solution. now, how long did it take from invention of cd to actually fully substituting tapes? at least in theory it always takes a new generation to introduce new technologies to the leading players. so be patient with adapteva...
as for architectual limitations, also here you shouldn't confuse limitations in hardware with limitations in software. epiphany programs are not in elf-format therefore there is no relocation-table. therefore you need to compile each program to be stored on a particular core. same with the setup I suggested: you'd need to write the administrative code on your own since this hasn't been done before. is that really a limitation in hardware? is a risc-architecture limited just because you're supposed to emulate in software or fpga what cisc processors do in hardware? epiphany is a risc processor with 32k cache per core but without actual cache-management on-chip! and if you choose to implement such cache-management in fpga, you'd end up wasting much more energy than if it's done in software. that's the whole point of risc in various aspects of its simplicity!