1024-core Epiphany-V news

[pgater]

Hi,

As I said on Adapteva's Linked In page, Ooooo I want one! Very exciting! Some questions though.

Will the chip be able to access external Dram as per the existing model? The reason I ask is that Contiki uses external ROM to keep parts of the system not used for that task out of working memory and I was hoping the external DRAM would fulfil that role.

The current Epihany chip needs a HAL and another processor to get data/instructions to run programs. Will the new chip be able to access data direct itself without the need for another CPU?

As the new chip has to be tested, that means designing a board so the chip can run. Is another test board that could be a Parallella board being designed?

Finally, work on my own little project (learning C and porting Contiki) has been proceeding rather slowly for various reasons. This announcement is a spur to get more done!

Regards,

Paul

[DonQuichotte]

This is by far the best news I've ever heard from Adapteva in 2015/2016 !

The 64 Kb will help a little 64-bit IALU will help quite much
The remaining challenges - power, heating, frequency, core initialisation... - are huge and I hope it will be successful.

I'd be proud to test one.
I've emailed a guy from Davis and no, the kilocore will never be mine not intended to be sold ; lol had to try it !

Best wishes for this ambitious project

[xilman]

The PDF has some interesting material but is a little light on detail when it comes to the extended instruction set. It seems a fair bet that 64-bit addition and multiplication are provided, but what about division and support for multiple precision arithmetic? These are areas where the present architecture has very serious shortcomings for most everything outside the DSP market.

[theover]

Exciting times where big ol Darpa want to promote the higher speed of creating processor architectures.

Reminds of the supercomputing classes where you learn about how to use all the bandwidth of all the cores all the time, or how to make sure your processor elements perform to either the maximum of the individual capacity or their collective highest temperature. It's also nice to put processors off the save power and to maybe include an FPGA image in the programming loop.

T.V.

[dobkeratops]

Wow, I missed this, (brexit has me preoccupied etc).
64k per core seems like a nicer balance.

[1] 'binary compatible with E4' - does that mean they're not pursuing RISC-V anymore? (no matter, epiphany is a nice ISA, I do like shared int/float registers)

[2] 'instruction set extensions for deep-learning and cryptography' ..
[2.1] might there be low-precision arithmetic e.g. 8x8bit in a single register,
[2.2] .. or indeed 'population count instruction' (I was interested in this for single-bit NNs, but I gather that shows up in cryptography too)

Q3 .. what would this end up costing in a parallels-like board? is there one on the way. Would this be competitive with say the nvidia and movidius chips (see fathom USB stick) aimed at AI for drones. On paper the epiphany scratchpad grid idea should be awesome for this role.

Q4 were there any enhancements/fixes to atomic ops (i think there were restrictions like not being able to do atomic ops between chips or something)

[jar]

[dobkeratops]

Not a US citizen unfortunately.
I guess the compatability and similarity keeps the existing board relevant as a development tool, maybe I can reconsider getting one. Nice to know the architecture can grow.
(the validity was never in any doubt and it was interesting to see other similar things appearing like the chinese supercomputer chip).

I look forward to future developments...