Documentation Errors

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Documentation Errors

Postby tono » Mon Dec 17, 2012 10:00 pm

I thought I start a thread for documentation errors.

First a very minor one:
In Epiphany Architecture Reference (G3), REV 3.12.10.03.
On page 62, The table 21, "Pipeline Stage Description", seems to be missing stage 7 (but have a stage 9).
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Re: Documentation Errors

Postby aolofsson » Mon Dec 17, 2012 11:42 pm

Great! Just fixed it. I owe you a beer :D
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Re: Documentation Errors

Postby Watse » Tue Dec 18, 2012 7:23 am

aolofsson wrote:Great! Just fixed it. I owe you a beer :D


A beer for every error we find?
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Re: Documentation Errors

Postby aolofsson » Tue Dec 18, 2012 12:49 pm

Nice try :D It's going to be hard to make beer a formal reward. Too many disclaimers needed.
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Re: Documentation Errors

Postby jar » Tue Dec 18, 2012 1:42 pm

aolofsson wrote:Great! Just fixed it. I owe you a beer :D

While now that beer might be involved...

From Rev. 3.12.10.03 page 54 Table 16: Integer Instructions
It seems IADD, ISUB, IMADD, IMSUB, IMUL have been neglected from the integer instruction table.
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Re: Documentation Errors

Postby timpart » Fri Dec 21, 2012 7:57 pm

In Epiphany SDK reference 3.12.10.3
Page 9 "compl" should be "complete." (might be meant as a joke.)
Page 42 "scree" should be "screen" (unless developing on the side of a mountain)

Regards,

Tim

P.S. Personally I wouldn't put IADD etc in the integer instruction table as it could cause confusion as to when they can be used.
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Re: Documentation Errors

Postby timpart » Thu Jan 03, 2013 10:22 pm

Thanks for the instruction set decode in Arch Ref 3.12.12.18

Page 129 Table 37
SUB I presume the value 1 means subtract.
S (bit 4 in LDR/STR) isn't documented. 0=Load, 1=Store?

Page 130 Table 38
The 3rd line of the load/store section is described as "LDR/STR (PM-IMM) (16)". Should this be "LDR/STR (PM) (16)"? Bits 7 to 9 contain Rm0 to Rm2 not I0 to I2, and there is no IMM3 mentioned on page 107
The 4th line of the load/store section is described as "LDR/STR (DISP) (16)". This should end (32).

Regards,

Tim
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Re: Documentation Errors

Postby aolofsson » Mon Jan 07, 2013 2:10 am

timpart wrote:Page 129 Table 37
SUB I presume the value 1 means subtract.
S (bit 4 in LDR/STR) isn't documented. 0=Load, 1=Store?

Page 130 Table 38
The 3rd line of the load/store section is described as "LDR/STR (PM-IMM) (16)". Should this be "LDR/STR (PM) (16)"? Bits 7 to 9 contain Rm0 to Rm2 not I0 to I2, and there is no IMM3 mentioned on page 107
The 4th line of the load/store section is described as "LDR/STR (DISP) (16)". This should end (32).


Thanks for the feedback and helping to make the manual better!!

1.) Yes, 1 for SUB means subtract
2.) The S bit specifies load/store. S=1-->store, S=0-->load
3.) Yes, should be PM-index
3.) True, imm3 will be added to the table.(was a bit of a hack..)
4.) Yes, typos acknowledged, will be fixed.
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Re: Documentation Errors

Postby mrgs » Sun Jan 13, 2013 6:10 pm

* BASED ON : epiphany_arch_reference_3_12_12_18.pdf :
* typo : @page 33 : the MEMPROTECT reg address is : 0xF0608 not 0xF0704
* typo : @page 40 : Table 8 : End Addr is 0xFFFFF not 0FFFFF
* typo : @page 49 : Table 12 : in header: 3rd column is : Mnemonics not Flags, 4th is Affected flags not Comment
* typo : @page 54 : Table 15 : (R)ow1, (C)olumn4 unnecessary comma, R2, C4 little 'd', R4, C4 little 'd', R5, C2 unnecessary semicolon
* typo : @page 55/56/57 : Table 16/17/18 : C4 : little 'd', 'n', 'm' + Table 18 : C4 : Missing hyphen at Multiply-Add and -Subtract
* typo : @page 58 : Table 19 : C4 : little 'd', 'n', 'cond'
* typo : @page 75 : First row of example missing '#' before immediate operand (mov R1, #0x08)?
* typo : @page 75 : wrong descriptor 'structure'?! .word v.s. .halfwords?! Well, maybe I misunderstand Table32 [and|or] assembly code?! Missing DMA CNT?! (!) PLZ. FIXME Sorry for my 'pseudo' assembly for better understanding?!
Code: Select all
* (!) ?!
 * mov R1, #0x08            ; STARTUP bit @ DMA0CONFIG                                     (!) FIXME
 * movt R1, _DMA0DESCRIPTOR ; My DMA descriptors for NEXT_PTR [32:16]
 * movts DMA0CONFIG, R1     ; Start DMA
 *
 * _DMA0DESCRIPTOR;
 *       .halfword16 0x0003    ; DMACONFIG
 *       .halfword16 0x0101    ; NEXT_PTR
 *       .word32 0x0001_0008   ; STRIDE-INNER
 *       .halfword16 0x????    ; CNT-INNER      You should set it at least 0x0001
 *       .halfword16 0x????    ; CNT-OUTER
 *       .word32 0x0000_0000   ; STRIDE-OUTER
 *       .word32 0x0000_2000   ; SRC ADDRESS
 *       .word32 0x9200_0000   ; DST ADDRESS
 *
 * OR: Depend our DMA needs...                                                            (!) FIXME
 *
 * mov R1, #                ; for DMA0STRIDE
 * mov R2, #                ; for DMA0COUNT
 * mov R3, #                ; for DMA0SRCADDR
 * mov R4, #                ; for DMA0DSTADDR
 * mov R0, #0x03            ; for DMA0CONFIG
 * movts DMA0STRIDE, R1     ;
 * movts DMA0COUNT, R2      ;
 * movts DMA0SRCADDR, R3    ;
 * movts DMA0DSTADDR, R4    ;
 * movts DMA0CONFIG, R0     ;

* typo : @page 127: Table 34 : C4 : repeated Address but missing comment column

* SUGGESTIONS:
* - Table 14-20 : You can eliminate the column 'Flags' with a note for each table regarding to the affected flags.
| OS4E : A preemptive, multiprocessing, microkernel based OS for Epiphany ARCH |
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Re: Documentation Errors

Postby ysapir » Mon Jan 14, 2013 4:50 am

@mrgs,

Programming and activating the DMA engine should be done using a descriptor. You should not program the DMA registers directly (except for DMACONFIG).

According to Table 32, next-ptr, stride (inner/outer, src/dst) and count (inner/outer) are all 16-bit values. The source and destination addresses are 32-bit each and can point to anywhere in the memory space.

Thus, in the sample descriptor, the configuration is to transfer bytes as a master w/o chaining DMA's. The strides for the inner loops are both 1 (meaning, a contiguous vector in memory), the inner loop count is 8 for transferring 8 bytes and the outer loop has only one iteration (so we transfer a 1-D contiguous array of bytes). The outer stride is not important here since there is no outer loop. Two values of 0 are just arbitrary. The addresses show copy from internal to external memory.

Once the DMACONFIG register is written with this descriptor's address and with a kick-start signal, the transfer begins.

Note that the descriptor's memory must not be altered while the transfer is in progress, or some undefined behaviour will occur :!:

BTW, the # prefix for immediates is not mandatory and is a matter of style.
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