Documentation Errors

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Re: Documentation Errors

Postby aolofsson » Sun Jul 14, 2013 11:45 pm

Gravis, Thanks for the detailed review and error finding!! All fixes will make it into the next architecture manual revision.
Andreas
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Re: Documentation Errors

Postby Gravis » Mon Jul 15, 2013 3:42 am

aolofsson wrote:Gravis, Thanks for the detailed review and error finding!! All fixes will make it into the next architecture manual revision.
Andreas

it's easy to find errors when you are reading every page to make an emulator. :P
just be sure that the fixes are actually proper fixes as information for fixing the opcode table was extrapolated.
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Re: Documentation Errors

Postby Gravis » Mon Jul 15, 2013 4:04 am

arch ref version: 3.12.12.18

Documentation Errors

---------------------------------------------------------------------------------------------

page 125) TESTSET instruction
multiple locations in "Operation:"
[RN+RM]

should be
[RN +/- RM]
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Re: Documentation Errors

Postby Gravis » Tue Jul 16, 2013 2:31 am

arch ref version: 3.12.12.18

Documentation Errors

---------------------------------------------------------------------------------------------

page 86 to page 97 (floating point instructions)
in "Operation" section
if (UbiasedExponent(RD) < -126) { BUS=1 } else { BUS=BUS}

should be
if (UnbiasedExponent(RD) < -126) { BUS=1 } else { BUS=BUS}
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Re: Documentation Errors

Postby Gravis » Tue Jul 16, 2013 11:50 am

arch ref version: 3.12.12.18

in Figure 14: Interrupt Service Routine Operation shouldnt the GIE & ~IMASK[N] & ~|IPEND[N:0] step have "NO" going back to the start of the ILAT[N] SET step? if not, wouldn't it mean that when an IRQ is set (while disabled) that unsetting it (while still disabled) won't prevent it from executing when it's enabled?

e.g.
Code: Select all
GID ; disable interrupt signals
MOV R0, #1
MOVTS ILATST, R0; set interrupt
MOVTS ILATCL, R0; clear interrupt
GIE ; enable interrupt signals
; interrupt signal is sent here even though the latch was cleared


should it be "GIE & ~IMASK[N] & ~|IPEND[N:0]" or is the "|" a typo and should be "GIE & ~IMASK[N] & ~IPEND[N:0]"? i'm not sure if this is some other language's syntax or what.
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Re: Documentation Errors

Postby LamsonNguyen » Sat Jul 27, 2013 5:02 am

epiphany_sdk_reference.4.13.03.301.pdf

section 3.1:
Similarly, C11 and C++11 are new standards and their partial is partial.

should be
Similarly, C11 and C++11 are new standards and their support is partial.


section 5.5:
........per-symbol, per-file, and per -object library.

should be
........per-symbol, per-file, and per-object library.


section 9: I think the first and third sentences can be concatenated.

section 9.1:
The input to the loader is a compiled and linked Epiphany program, that was generated by e-gcc/e-ld.

should be
The input to the loader is a compiled and linked Epiphany program generated by e-gcc/e-ld.


section 9.2:
Load program onto the target, on a 4×4 block of cores starting at core 0x808 (32,8) and start it immediately after:

should be
Load program onto the target, on a 4×4 block of cores starting at core 0x808 (32,8), then start it immediately afterwards:


table 9.1:
With this option set, the loaded programs are started after finished loading on all cores in workgroup.

should be
With this option set, the loaded programs are started after they have finished loading on all cores in the workgroup.


Path to the program image to load on the core workgroup.

should be
Path to the program image to load onto the core workgroup.
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Re: Documentation Errors

Postby ysapir » Sat Jul 27, 2013 8:02 am

@LamsonNguyen,

Thanks for your comments.
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Re: Documentation Errors

Postby timpart » Sat Jul 27, 2013 9:08 am

Architecture Reference Manual I'm looking at 4.13.01.14 The Adapteva website latest documentation has an out of date link to 3.12.12.18

In 4.2 I found parts of the discussion memory transaction ordering a bit confusing. Perhaps some examples with diagrams could be added after table 1 to make it clearer?

It says Load operations using data previously written use the updated values.
Does that mean written into a local register?
Table 1 says write to Core X followed by read from Core X is non deterministic. which contradicts this.

Also could you have a little table indicating which which instructions are Read and which are Write for the purposes of Table 1.
I presume LDR and TESTSET are Read and STR is write. The documentation for TESTSET is not clear on this point, but to my mind feels more like a Read with side effects.

I presume the reason that Read from X followed by Write to X is deterministic is that the core stalls until the Loaded data are returned? Otherwise the Write could easily overtake the Read if the loaded register wasn't referenced immediately.

EDIT: The Adapteva web site also calls version 4 of the SDK reference the latest, but I have 5.13.07.10 (from git hub)

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Re: Documentation Errors

Postby Gravis » Sat Jul 27, 2013 1:34 pm

timpart wrote:Architecture Reference Manual I'm looking at 4.13.01.14 The Adapteva website latest documentation has an out of date link to 3.12.12.18


you have your documents mixed up. here's the latest:

Epiphany Architecture Reference Manual - 3.12.12.18
Epiphany SDK Reference Manual - 4.13.03.301 <-- i think you were looking at a slightly earlier version of this
Epiphany-III Datasheet - 3.13.6.14
Epiphany-IV Datasheet - 4.13.6.14
Parallella Reference Manual - 4.13.2.13
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Re: Documentation Errors

Postby ysapir » Sat Jul 27, 2013 3:17 pm

Gravis,

The latest SDK reference is actually 5.13.07.10 that is included with the latest SDK release. You are probably referring to the document that appears in the website, and we should update that.
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