Parallella Community

I thought I start a thread for documentation errors.

First a very minor one:
In Epiphany Architecture Reference (G3), REV 3.12.10.03.
On page 62, The table 21, "Pipeline Stage Description", seems to be missing stage 7 (but have a stage 9).

Great! Just fixed it. I owe you a beer

Nice try It's going to be hard to make beer a formal reward. Too many disclaimers needed.

In Epiphany SDK reference 3.12.10.3
Page 9 "compl" should be "complete." (might be meant as a joke.)
Page 42 "scree" should be "screen" (unless developing on the side of a mountain)

Regards,

Tim

P.S. Personally I wouldn't put IADD etc in the integer instruction table as it could cause confusion as to when they can be used.

Thanks for the instruction set decode in Arch Ref 3.12.12.18

Page 129 Table 37
SUB I presume the value 1 means subtract.
S (bit 4 in LDR/STR) isn't documented. 0=Load, 1=Store?

Page 130 Table 38
The 3rd line of the load/store section is described as "LDR/STR (PM-IMM) (16)". Should this be "LDR/STR (PM) (16)"? Bits 7 to 9 contain Rm0 to Rm2 not I0 to I2, and there is no IMM3 mentioned on page 107
The 4th line of the load/store section is described as "LDR/STR (DISP) (16)". This should end (32).

Regards,

Tim

@mrgs,

Programming and activating the DMA engine should be done using a descriptor. You should not program the DMA registers directly (except for DMACONFIG).

According to Table 32, next-ptr, stride (inner/outer, src/dst) and count (inner/outer) are all 16-bit values. The source and destination addresses are 32-bit each and can point to anywhere in the memory space.

Thus, in the sample descriptor, the configuration is to transfer bytes as a master w/o chaining DMA's. The strides for the inner loops are both 1 (meaning, a contiguous vector in memory), the inner loop count is 8 for transferring 8 bytes and the outer loop has only one iteration (so we transfer a 1-D contiguous array of bytes). The outer stride is not important here since there is no outer loop. Two values of 0 are just arbitrary. The addresses show copy from internal to external memory.

Once the DMACONFIG register is written with this descriptor's address and with a kick-start signal, the transfer begins.

Note that the descriptor's memory must not be altered while the transfer is in progress, or some undefined behaviour will occur

BTW, the # prefix for immediates is not mandatory and is a matter of style.