Parallella Memory

[grzeskob]

Hi,

I am trying to understand the Memory architecture of Parallella. Unfortunately I have less knowledge of VHDL and can not readout details from hw files. I will be grateful for comments if I misunderstand something.

According to documentation and posts I could summarize:
There are 3 sorts of RAM available in system [2]
1. Host Ram
Q1. Is it "O/S DRAM" from Figure 4. Reference Manual (marked as Off-Chip), or On-Chip Memory described in Ch.29 Zynq-7000 Technical reference manual ? Where can I find the details about this memory. Size, address, accessibility etc.
2. Shared Ram
Shared RAM memory - 1 GB 32-bit - accessible for both Dual-core ARM and each epiphany core
Described as SHARED DRAM on Figure 4. Reference Manual
3. Epiphany local Ram
16 x 32 kB accessible for Dual-core ARM and each epiphany core
Described as Epiphany on Figure 4. Reference Manual

Dataflow:
Q2. Data between epiphany cores is exchanged via rMesh and cMesh. It might be also exchanged via shared Ram, but it does not have a lot of sense considering bad performance.

"The Epiphany coprocessor is connected to the Zynq SOC via the 48-pin eLink interface" [1].
Q3. Does eLink interface have anything to do with eMesh NOC ? If not, how are the data transferred from elink to particular epiphany core ?
Q4. Data exchange between Epiphany and Shared Ram goes through eLink<->FPGA<->MEM-CTRL<->Shared Ram without any ARM DualCore interaction ?
Q5. All data exchange possibilities between ARM DualCore and Epiphany are :
- ARM can send binary (code and data) to epiphany via eLink
- ARM can read Epiphany local Ram via eLink
- ARM can read/write to shared memory via MEM-CTRL
- Epiphany can read/write to shared memory according to Q4
- Epiphany can not read/write from/to Host Ram

References:
[1] Epiphany Architecture Reference
[2] ()

[sebraa]

Host DRAM is probably the "O/S DRAM", although I have not checked this detail. I don't think this matters. It is 1 GB in size. Shared DRAM is located in the same "Host RAM", and just a 32 MB part of it. Local RAM is 32 KB in size and inside each Epiphany core.

The Epiphany cores exchange data with the rMesh, cMesh and xMesh only. The external hardware interface to the mesh (available on the pins) is called eLink.

The eLink interface is implemented in the FPGA logic of the Xilinx Zynq and connected to the AXI bus of the ARM cores inside the Xilinx Zynq. There is probably no software involved when transmitting between Epiphany and Shared DRAM.

This is my understanding of it. If I'm wrong, please correct me.

[greytery]

Hi grzeskob,

First, the Epiphany is not the Parallella. (It's a bit like using the spec of an AMD graphics chip to determine how a PC's memory is managed).
The Epiphany manual is written from the view of the Epiphany which could be housed in any number of systems, of which the Parallella-16 is one example.
I suggest you check the . That will give you a better overview of how the Parallella memory works as a whole, from the point of view of the ARM/Linux/Host code and from the Epiphany viewpoint. On Parallella, the key is how the Zynq maps the memory.

Also, please read by timpart, which I found very useful.

Adding to sebraa's answer, my take is as follows ...
Q1. See Parallella manual.

Q2. If the dataset is so large that it exceeds the size of the Epiphany memory, then one way would indeed be to use the 32Mb shared RAM. And yes, the access speeds are considerably slower and that would need to be taken into account when designing Epiphany programs - and may not be worth the effort for some cases. (Note that the next version of the SDK is supposed to include a 'paging' facility for the Epiphany, so clearly it is thought that there will be some cases where that would be useful).

Q3. There is an eLink interface at each of the N,S,E & W edges which effectively terminates the eMesh. The eLink is supposed to be the interface between Epiphany chips and would pass the data through to the eMesh, which continues the routing according to the (row,col) coordinates. The Zynq implements an interface to the East eLink (the West eLink is not connected, and usually, nothing is connected to the North or South either). When the ARM writes to an address which maps to an Epiphany core the Zynq routes it to the East eLink, which passes it through to the eMesh - and then it's a question of what (row,col) coordinates are set.

Q4. Correct. The Zync maps the address used by the Epiphany (row,col) onto the address of the 32Mb shared memory.

Q5. Correct - if you expand 'eLink' to include the Zynq FPGA interface to the East eLink interface.
Also, the "Epiphany can not read/write from/to the Host RAM" i.e. the DRAM left after reserving the top 32Mb for Shared memory. The way that the Zync/eLink interface remaps the addresses coming from the Epiphany to the Host limits the access to that top 32MB. The translation code is mentioned .

Hope that helps,

[jrambo316]

[grzeskob]

[sebraa]

Reading from the mesh is much slower than writing. Although it is possible to execute code from anywhere in the address space, you should aim for local execution at least. You could copy the code to the local core first, though.

[greytery]

[cmcconnell]

[jrambo316]

Thanks for the informative responses. I did not know whether the slow external memory was due to the fpga interface or beyond it. If the weak memory model in the mesh is a problem with instruction order, how can programs be run solely in external memory, e.g. the legacy ldf?

[jrambo316]