Parallella Memory

[jrambo316]

In table 1 on page 20 of the epiphany reference manual, it describes the memory model. It seems to me that the read core x/ read core x and the read core x / read core y would be applicable here. Both were deterministic. What am I missing?

[cmcconnell]

[greytery]

[cmcconnell]

[Melkhior]

[aolofsson]

Just so that we are clear regarding point #2.

The following scenario is a gotcha!
[edit: Bad example below! Could only happen for DMA, not with regular LDR instruction]

1.) CoreA writes aa to addr X
2.) CoreA reads from addr X
3.) CoreA write bb to addr X

The value read back in step 2 could be aa or bb, depending on network traffic. Very likely that aa is returned, but not guaranteed

This is only an issue when X is outside coreA.

[edit: New example]
A more likely scenario is the following:
0.) CoreA writes aa to addr X
....a lot of other stuff happens
1.) CoreA writes bb to addr X
2.) CoreA reads from addr X
Lesson, don't set some kind of program status/sync flag outside of local memory, without doing an explicit path flush as described here:
viewtopic.php?f=49&t=984

[notzed]

[Melkhior]

[greytery]

[notzed]