increase shared memory

Discussion about Parallella (and Epiphany) Software Development

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Re: increase shared memory

Postby greytery » Sat Jun 14, 2014 7:09 am

Now we find that the device tree is ignored, and the real shared memory contraint is set in the bootloader (Das U-Boot) which makes thinks even more hairy to build. (Could still be done though).
But in the thread at http://forums.parallella.org/viewtopic.php?f=10&t=1069&start=20#p8438, we have an intriguing comment:

aolofsson wrote:fyi..the u-boot/kernel shared memory hack was just a temporary solution, we are now working on something more flexible and way coooler.:-)
Andreas

Watch this shared space!

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Re: increase shared memory

Postby schmurfy » Mon Jun 16, 2014 2:22 pm

While I don't understand everything said in this thread I think I got the most important, while I don't really need more than the 32MB right now (I am still playing with the board) having a way to extends it which does not involves recompiling the kernel or bootloader (that really sounds scary) would be really nice. The non contiguous part may be annoying but I think multiple cells of 32MB could still be useful if this can't be asbtracted.

For now I just reached the point where I have a program of my own running on the parallella and epiphany cores, I still have to figure out why the epiphany part is so slow (I need to look at the math optimization flags I think) and why the communications between the cores and the host is not entirely working as intended.
So as you see I still have some work/learning to do before I can really decide whether or not the 32MB are enough for me :D
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Re: increase shared memory

Postby TomV » Wed Dec 03, 2014 11:04 am

Just a random thought, but can't the (C/X/R)MESHROUTE register be used to divert all of-chip addresses to the EAST-side link?

In many cases this will become a lot slower, since traffic is routed all around the chip, but you could setup a router on a far-NORTH-EAST core to route all WEST and NORTH traffic EAST. Effectively disabling WEST-bound write communication on that core (NORTH was already off-chip), but giving that core, erhm let me think, for instance (0x00100000 – 0x80A00000) = 2057 MB of contiguouss DRAM address space. (not entirely true since the DRAM is only 1GB and doesnt extend beyond 0x3FF_FFFFF).

So you could sacrifice this one core to do all your external RAM handling. Not sure in what situations this might be usefull, but the idea is still interesting to me :P

( O, and I think there might be a copy-paste typo in the architecture reference for the MESHROUTE registers. EAST/WEST/SOUTH settings only influence NORTH-bound traffic according to the desciption....)

DISCLAIMER : I haven't actually played with the board yet, so I might be horribly wrong..
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