questions about the memory bandwidth

Any technical questions about the Epiphany chip and Parallella HW Platform.

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questions about the memory bandwidth

Postby yisaogua » Thu Nov 27, 2014 5:50 am

Hi all,
I tried to measure the Epiphany's data communication performance with my board, and found that the read bandwidth of epi_core-to-eRAM are not like i expected. I tested it with variable size data fetching, but the bandwidth never exceed 100MB/s. It fails to reach the claimed GB-level peak bandwidth of e-link, or that of the HP AXI port in Zynq end.
I guess the problem may be sourced to the emesh protocol that doesnt seem to support data burst request. The DMA or read request is decomposed into segmented emesh requests, so that the AXI slave port has to forward the decomposed burst reads and get responded by the dram memory for multiple times. If this is the case, the burst transmission mode of AXI cannot be exploited for bulk data read. So, if i want to solve the issue, Is it possible to do something with Zynq's PL to change the glue logics between e-link and AXI ports?
since I'm fresh to parallela, please correct me if i'm wrong.
Thank you.
FYI, I clip the measurement results in thread.
bandwidth (1)_页面_2.jpg
bandwidth (1)_页面_2.jpg (75.78 KiB) Viewed 4294 times

bandwidth (1)_页面_1.jpg
bandwidth (1)_页面_1.jpg (59.55 KiB) Viewed 4294 times
yisaogua
 
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Re: questions about the memory bandwidth

Postby aolofsson » Wed Dec 03, 2014 1:20 pm

yisaogua wrote:I tried to measure the Epiphany's data communication performance with my board, and found that the read bandwidth of epi_core-to-eRAM are not like i expected. I tested it with variable size data fetching, but the bandwidth never exceed 100MB/s. It fails to reach the claimed GB-level peak bandwidth of e-link, or that of the HP AXI port in Zynq end.

The GB-level peak bandwidth is for the Epiphany chip, not for the Parallella platform as a whole. To get to 2GB/s peak elink bandwidth applies to an 1 GHz Epiphany chip doing streaming writes. (this should be stated throughout the datasheets/docs, aplogies if this is not clear enough). Doing reads or non consecutive writes will cause this bw to drop by 75%. The TX out of the Epiphany runs at the core clock divide by 2. So in the case of the parallella, where the Epiphany runs at 600MHz, the peak bandwidth is 600MB/s out. The RX runs into Epiphany runs at whatever clock the sender runs at. In the current case, this is 150MHz?. In the new eLink that is soooo close to being released, this has been increased to 500MHz, meaning that you will soon be able to push data into the Epiphany at a rate of 1GB/s (if the eLink was the only bottlneck).

yisaogua wrote:I guess the problem may be sourced to the emesh protocol that doesnt seem to support data burst request. The DMA or read request is decomposed into segmented emesh requests, so that the AXI slave port has to forward the decomposed burst reads and get responded by the dram memory for multiple times. If this is the case, the burst transmission mode of AXI cannot be exploited for bulk data read. So, if i want to solve the issue, Is it possible to do something with Zynq's PL to change the glue logics between e-link and AXI ports?


The right way to solve this issue is to either create a DMA in the PL (the way ADI did for the HDMI) or to use the PS DMA to pull data from DRAM into the Epiphany. Doing thousands of individual DRAM reads from the Epiphany is not a good model. This is something that we (or others) will do as soon as the new eLink has been released...

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