Timer strangeness

Any technical questions about the Epiphany chip and Parallella HW Platform.

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Timer strangeness

Postby sebraa » Mon Jul 27, 2015 7:46 pm

I found some strangeness around the timers, and I am not sure what to make of them:

(1) My timers get their configuration changed and I have no idea why.

I wrote a program (source available here) which reads the CONFIG register and shows the current timer configuration and values. Also, I use a program which uses barriers and accesses to shared memory (source available here). If I set up timer 1 to "Mesh traffic monitor 1" (all config bits set) in each iteration and watch the timer configurations while the program is running, it changes constantly (including to the reserved values 3 and 9), so something is going on with the CONFIG register. Even if all cores run the same code, the changes are different for each core. If I do not constantly reset the timers, then they will end up at "Off" after an unspecified amount of clock cycles.

If I do not set up the timers in my Epiphany program, but change the timer configuration from the outside (by halting the core, changing CONFIG, resuming the core), then the timer gets turned off after some unspecified time. I've seen counter values of 5 or 10 million until it changes from CLK to OFF. This also happens in another program which does not use barriers. Of course, when the code changes the FPU mode, then the CONFIG change will be reset immediately, but not after millions of clock cycles.

(2) What do the Reserved timer values measure?

I noticed that the random bit flipping in the CONFIG register (not in my code) also changes to the reserved values 3 and 9. Also, there is some interaction... if I set timer 1 to "Reserved (3)", then timer 0 will wrap around. This makes timer 0 more useful, at the cost of random values in timer 1. :-)
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