2200vm - An emulation of OS 2200

[dms1guy]

1. Background
Apple has successfully used Dynamic Binary Translation (DBT) to port their software base from a 68000 platform to a PowerPC platform, and then again to an x86 platform.

I had the pleasure of working for Transitive in Manchester, UK during the period when Transitive delivered the Rosetta product for Apple which enabled Mac PowerPC Apps to run on x86. Transitive were eventually acquired by IBM.

2. Unisys looks to port 2200 apps to Itanium
Shortly after Intel announced Itanium 2, Unisys explored shutting down their 2200 mainframe processor division and running their 2200 mainframe applications on Itanium using DBT. They initially developed an in-house 'interpreter' solution which worked, but was dog-slow. So they commissioned Transitive to develop a DBT solution. I had worked earlier on the 'IRIX on MIPS' to 'Linux on Itanium' translator and so ended up on the team tasked with delivering the 2200 to Itanium DBT product.

Whilst the translation model Transitive used worked well for x86, PowerPC, MIPS, ARM and that style of processor, it struggled with the 2200 processor (called the XPA Instruction Processor). The reasons were that the XPA saw memory as 36-bit words, could atomically access 18-bit and 9-bit sub-words, and had complex memory management registers,as well as 1's complement arithmetic and a whole host of other issues. The end result was a DBT engine that did not perform much better than the interpreter Unisys had developed.

3. The 2200vm Project is born
I had warned the team at Transitive that they needed a new DBT architecture, but I was voted down and the end result was exactly what I had warned about at the start of the project. This left me with a sense of "unfinished business" for many years, and I am still convinced that I can get XPA code to run well using DBT, but I have been waiting for the right target processor to be commercially available.

It is generally agreed within DBT circles that the best DBT target processors are VLIW architectures, hence Transmeta used a VLIW and Intel designed Itanium as a VLIW so it would be a good DBT target.

In my opinion, VLIW is the wrong way to go, and a many-core DSP-style processor, with directly addressable memory banks and short pipelines, like Epiphany is much closer to the ideal architecture.of a processor that could perform DBT optimally. The biggest bain of my life is cache. On the Itanium, there are 3 levels of cache. But for DBT, you need directly addressable on-chip memory.

So having completed my initial evaluation of the Epiphany architecture as a potential DBT target, I have decided to finally write the XPA-to-target DBTengine I have been itching to do for many years, and to use the 16-core Epiphany as the target.

4. Project Goals
Emulating just a CPU is not much use without an OS. So the emulation will include the core executive of OS 2200. The idea being to be able to run legacy 2200 apps on Epiphany.

I have named my project "2200vm" as it is a VIRTUAL MACHINE emulating an OS 2200 executive running on a Unisys 2200 mainframe.

At this stage I am doing this out of pure interest, to see how well my ideas on data-driven instruction scheduling hold up, and I intend to produce some benchmarks to compare the original Itanium 2 performance ( 1.6 GHz, 128-bit data paths ) with the Parallella board (600 MHz, 64-bit data paths ). Whilst it looks a bit of a David vs Goliath situation, I suspect the end results could raise some eyebrows.

Once I have a basic working DBT engine running, it is my intention to produce a web-based console so that anyone who wishes to have a play, or run their own benchmarks can have a go at running a mainframe emulation on a Parallella board. I also intend to post any relevant updates to the project on this thread.

In any event, I have just launched the project and just wanted to raise awareness of my project to the Parallella forum members in case anyone has any interesting ideas, thoughts or observations they would like to share on this project, or on DBT on Epiphany in general.

[dms1guy]

[dms1guy]

[dms1guy]

[jar]

Sounds like an interesting project, and fortunately the Epiphany has a surplus of registers. Have you performed any analysis to determine the size of the translated binary relative to the original binary? I would think that, for the memory constraints of this architecture, it may be more effective to use direct threaded dispatch in some cases rather than DBT. My thoughts are that the minor dispatch overhead would be smaller than additional off-chip memory accesses due to a larger translated binary.

[dms1guy]

[dms1guy]