Parallella PEC GPIO LVDS Voltage

[metinburak]

Hi all,

We are using the Parallella board embedded platform.

When it comes to the BLVDS connection of PL side to external interfaces via the PEC GPIO connectors, we see that the pins on the PEC GPIO are from Bank 34 and Bank 13 (http://www.parallella.org/docs/parallella_schematic.pdf)

When we look at these banks (http://www.xilinx.com/support/documenta ... lectIO.pdf), the Bank 34 is HP and the Bank 13 is HR.
And when we look at the SelectIO, we should use HP with 1.8V and HR with 2.5V for (B)LVDS.

So, first question is -is there anybody used the GPIO connector of Parallella for bidirectional LVDS? If so, what was the voltage? 2.5V for both Bank 34 and Bank 13?

Second question iis -if we should use 1.8V for Bank 34 and 2.5V for Bank 13, how can we accomplish this as there is only 1 VddGPIO in the PEC GPIO?

PS:
XILINX says that the HP can only work with 1.8V for LVDS
http://www.xilinx.com/support/answers/43989.html

and we know that HR needs 2.5V for LVDS

I'm also confused because I can use Zedboard's FMC connector utilizing Bank 34 and Bank35 in LVDS_25 mode, despite Xilinx says that HP ports can not be used in LVDS_25.


Thanks in advance.
Burak.

[tnt]

The pinout for the 7020 in there :

http://www.xilinx.com/support/documenta ... Pinout.pdf

shows that there are no HP banks at all, they're all HR.

[metinburak]