Epiphany memory map

Any technical questions about the Epiphany chip and Parallella HW Platform.

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Epiphany memory map

Postby msweep » Tue Dec 08, 2015 6:56 am

Hello,

I'm very new to Parallella board and Epiphany chip, so I'd have some questions about both the chip and the board.

I've read some documentation, and have some remaining questions.

Could anyone confirm that each byte in the 32 KB local memory can be accessed by two addresses? The first, local address, is with the 12 high order bits set to zero, in the range 0-1 MB. The second is with the core's position in the grid set in the 12 high order bits, with the same values for the low order bits.

If this is correct, then how can be accessed the memory of core (0,0) by any other core? Because then the external addresses are confused with the local ones for each core.

Thank for your answers!
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Re: Epiphany memory map

Postby sebraa » Tue Dec 08, 2015 1:48 pm

Each core is allocated a 1 MB slice of address space (which contains the 32 KB SRAM, some memory-mapped registers and a lot of reserved space). You are right: For each core, the very first MB of address space always mirrors its own address space. However, in the global address space, there is no core (0,0); each Epiphany chip has some physical pins which decide the location of its cores in this global address space.

On the Parallella, only the cores between (32,8) and (35,11) inclusive exist. So there is no address space clash.
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Re: Epiphany memory map

Postby msweep » Tue Dec 08, 2015 5:57 pm

Thank you for the confirmation!

My question about core positions was more theoritical than practical.
I should have written: if the Epiphany chip was remapped from position (32,8) to (0,0), would that prevent acessing the memory of the first core (the one now at absolute position (0,0))?

Seems to me that yes, because the dual mapping of the address space would make "global" inter-core address the same as "local" internal ones. Or did I miss something?
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Re: Epiphany memory map

Postby sebraa » Wed Dec 09, 2015 2:53 pm

Well, at least core (0,0) could access itself. ;-)
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Re: Epiphany memory map

Postby peteasa » Wed Dec 09, 2015 7:15 pm

With the porcupine board you get access to the id bits so you can, and I have, reposition the set of cores. Then after re-positioning you get to understand that 0x810 core address used for the elink fpga connection has a significance! Also the routing algorithm that routes to the east first then on the north south track. But you could re-build the fpga elink connection and have the elink fpga link address defaulted but able to be configured... then also you can use remapping in the elink to do some stuff... Not sure if all of that gains you anything unless you get your hands on a relatively large number of parallella boards! Never the less intellectually interesting!
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